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Deciso delivers new open source firewall alternative

By releasing the full potential of the AMD G-Series SOC for wire speed gigabit network security it is now possible to protect networks with affordable and turnkey open source firewall appliances. The new OPNsense firewall appliances provide an easy-to-use yet powerful platform to users and developers. Its source code is open and verifiable for all.
The AMD G-Series SOC made it possible to design a product without bottlenecks that is stable, cost effective and durable. ... Read more Read more
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MIPS P5600 CPU sets new record for embedded processing performance

By Alexandru Voica
December 17, 2015 in MIPS Processors, Processors
Two months ago I was returning home from our first ever Imagination Summit in Japan. While waiting to board the
airplane that would take me back to England, I saw a billboard sign for Nissan – “WHAT IF_the world’s fastest man went even faster?”. That’s an
interesting question, I said to myself. A few weeks later a new email arrived in my inbox from my colleagues in the engineering team informing me that MIPS P5600 had entered the CoreMark chart straight at the top with
a record-breaking score of 5.6 CoreMark/MHz per CPU.
http://blog.imgtec.com/mips-processors/mips-p5600-cpu-sets-new-performance-record

The world’s fastest single-threaded CPU had gone even faster.


This increase in performance was no accident. Like Nissan, we have always been driven to beat the best, even when the best is ourselves; P5600 is now the new king of CoreMark, beating the previous top score held by our award-winning MIPS proAptiv processor.

MIPS P5600 offers 20% more raw performance in a smaller area
The result has also been certified by EEMBC, the premier and long-standing embedded processor benchmarking consortium that designs and maintains CoreMark; you can find the complete list of certified results on their website.
To put this new result into perspective, a MIPS P5600 CPU delivers 20% more performance than its direct competitor while being significantly smaller in area.
MIPS P5600 even scores higher in CoreMark/MHz than Intel’s desktop line of CPUs. For example, an Intel® Core™ i7-2640M processor achieves 14513.79 CoreMark at 2.8GHz, or 5.18 CoreMark/ MHz – nearly 10% lower than the latest result for MIPS P5600.

MIPS P5600 has the highest certified CoreMark score of all licensable CPUs


This unprecedented level of performance efficiency will offer a welcome boost to MIPS-based embedded processors used for power-sensitive applications such as mobile, home entertainment, networking, automotive and many others.
Even more importantly, these outstanding results have been achieved using the latest off-the-shelf GCC compiler.
All of our customers can access this high-performance toolchain either as source from partners or packaged in SDKs from Imagination. This approach is in contrast with some of our competitors that achieve their best benchmark scores with expensive, closed-source toolchains.
Instead, Imagination is focused on building an open ecosystem that delivers performance quickly and painlessly, an important consideration for reducing time-to-market in mobile and embedded applications.

A quick recap of MIPS P5600


P5600 is a member of our MIPS Warrior P-class processor family and targets ultimate performance for mobile and embedded applications.
P5600 is a 32-bit CPU based on Release 5 of the MIPS architecture and includes a series of unique features such as:

• A fast 128-bit SIMD engine for accelerating multimedia processing and other matrix-type operations
• Full hardware virtualization supporting multiple fully isolated guest operating systems running in parallel.
• Enhanced security for consumer and enterprise applications; this includes the ability to support multiple TEEs (Trusted Execution Environments) on a single CPU.
• Best in class, advanced branch prediction mechanisms, page table walking hardware in TLB for optimal performance, instruction bonding for up to 2x increase on memory
-intensive data movement routines
• Enhanced Virtual Addressing (EVA) for more flexible usage of virtual address space, providing easy and efficient use of memory; eXtended Physical Addressing (XPA) support to fully utilize up to 1 Terabyte of memory (40-bits)


MIPS P5600 features a powerful, feature-rich micro-architecture
This high-end MIPS CPU is also part of our third generation of multi-issue, OoO (Out-of-Order), fully synthesizable processors; the figure below illustrates the evolution of high-performance MIPS CPUs over time, from 74K and proAptiv to present day.
MIPS P5600 features a series of improvements over previous generation proAptiv CPUs, including enhanced fetch efficiency, reduced L2 cache latency and pre-fetching; additionally, improvements in cache replay and memory disambiguation contribute to gains in performance for a wide variety of real world-applications (e.g. memcopy performance).
We are very proud of the record-breaking results in performance that the new MIPS Warrior CPUs continue to deliver.
This achievement is built on a heritage of designing high-performance MIPS CPUs; advancements in instruction set architecture (e.g. Release 6) and memory subsystems together with the continuous innovation in micro-architecture implementations will lead to even better results.
By combining MIPS Warrior CPUs, PowerVR multimedia IP and Ensigma connectivity IP, system engineers can design state of the art embedded processors that deliver best in class performance at lower power consumption and smaller area; you can read more about building highly competitive platforms using our hardware IP here [ http://blog.imgtec.com/multimedia/building-next-generation-apps-processors-for-mobile-computing ] and here [ http://blog.imgtec.com/powervr/chipsets-for-smart-glasses-and-other-high-end-wearables ].

The evolution of high-end 32-bit MIPS CPUs
If you want to get the latest news and updates about MIPS, make sure to follow us on Twitter (@ImaginationPR, @MIPSGuru, @MIPSdev), Facebook and LinkedIn. For those interested in knowing more about CPU benchmarks, come back to our blog for an upcoming article detailing CoreMark, DMIPS and other industry benchmarks.

Imagination Technologies
www.imgtec.com
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An introduction the ‘Sudden Impact’ Series

The wearable fitness market is entering a new phase and with the industry predicted to be worth $12billion by 2018, there is the opportunity for manufacturing and technology firms to establish themselves as market leaders. It is time for these businesses to take an active role and enable innovative solutions to promote healthier living, prevent injuries and ultimately, save lives.


This is the first in a series of exclusive blog posts for EP&Dee that will explore the challenges of designing wearable medical devices, inspired by elemenet14’s new ‘Sudden Impact’ Wearable Design Challenge.

Inspiring a generation


To kick-start this proactive approach, at element14 we have challenged our 280,000 strong online Community of design engineers and hobbyists to get involved in the ‘Sudden Impact’ Wearable Design Challenge. We asked our participants to create unique technological solutions that provide real-time, critical insights to a user group that would benefit from these specific capabilities – athletes.
Equipped with a range of advanced tools including a single-lead heart rate monitor, advanced protection polymers and a temperature sensor, our participants will also have access to support from Tektronix, Electrolube and Analog Devices and a $500 budget for any additional parts they may need. With the appropriate tools and right level of support, we aim to inspire designs that will one day have a widespread reach to athletic environments across the globe.

From concept to creation


The twelve designers proposed some fantastic ideas and we’re looking forward to watching them develop. While simple devices that monitor and relay uncomplicated data are prevalent in the wearable and fitness market, the designs our participants are creating are aimed at specific sports. With this level of specificity, athletes would be able to customise their device and training programme accordingly.
Designers in this area include Cosmin Iorga from the US who is building head, foot and arm modules for tennis players to track their body temperature, heart rates and blood oxygen amount, as well as their dehydration and exhaustion levels.
Meanwhile, Norbert Kovacs from Hungary is designing smart clothing for bikers that can log their heart rate, body temperature, acceleration and even provide an analysis of their journey.
Another focus for our designers is on the impact-related injuries that are most common within a specific sport.
Notorious for accidents, skiing has been a common theme as Germany-based Hendrik Lipka shows with his helmet-mounted impact monitor, aimed at tracking skiers’ heart rates as they hit the slopes.
This group also includes two designs inspired from India, both aimed at footballers. While Shubham Garg is developing a system to monitor fatigue and internal bleeding, Ravi Butani aims to measure chest, head and spinal injuries amongst American football players.

Impact measurement


These ideas, along with the others, will be thoroughly tested by the School of Computing, Creative Technology and Engineering at Leeds Beckett University. Each design will be judged on how well they meet the following criteria: effective use of the equipment, ease of use for a secondary school pupils, durability against various athletic grounds and arguably the most critical – the device’s ability to provide medical professionals with valuable and accurate diagnostic information.
All twelve designs are currently in progress and the participants will be sharing their journey with blogs, videos and photos on the dedicated Sudden Impact Challenge page on the element14 Community.
In the next post, I will be delving deeper into the intricacies of the design techniques our participants are using to carry their designs from an idea into a functional prototype.

About the Author
Christian DeFeo is the e-supplier and innovation manager at Farnell element14, a global electronics distributor and online community of more than 280,000 design engineers and tech enthusiasts.

Recently, he oversaw the Beyond the Phone challenge in which element14 members developed wirelessly powered medical devices. He is currently leading the Sudden Impact design competition ■
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The power of three to increase digital power adoption

Digital power is becoming an increasingly important technology in our industry. Energy consumption is reaching extremely high levels worldwide and particularly so in Information and Communication Technology (ICT) and in data centers even more so. In addition to which, the increasing complexity of power distribution systems means that the flexibility of digital power can help with the sheer number of different voltage rails required for microprocessors, ASICs, FPGAs and other digital logic.



Author:
Patrick Le Fèvre,
Marketing and Communication Director at
Ericsson Power Modules

It was the development of off-the-shelf digital power converter modules that has accelerated the adoption of digital power over the past few years – the trend was kicked off back in 2008 when Ericsson launched the BMR453 intermediate bus converter. It has become readily apparent to those that look that digital control has been particularly successful in improving the efficiency of data network power systems. When data traffic demand is low, networks operate well below capacity and their processors can run at lower clock speeds. Accordingly, this means the power supplies are operating well within their capability, which in effect means they become relatively inefficient and results in excessive energy consumption and waste heat generation. By implementing a digital control loop encompassing both intermediate bus and POL (Point-Of-Load) converters, the intermediate bus voltage can be varied dynamically in response to varying loads. The input voltage to the POL converters is reduced under low-load conditions, which can mean significantly increased conversion efficiency. In addition to which, digital power devices are increasingly employing techniques such as dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) using open-loop and closed-loop approaches, respectively, to even more closely adapt the supply near to the minimum voltage required by the processor, and in the case of AVS also compensating automatically for temperature variations in the processor.
These advanced capabilities have led to the wider adoption of DC/DC power modules, which in turn has meant increasing demands for the standardization of products from different manufacturers, especially for reasons of supply-chain reliability and second sourcing. This has led to the formation of trade associations including power supply and component vendors. However, these alliances have resulted on little more than the specification of standard footprints and pin-outs for certain categories of power converter, such as non-isolated and isolated DC-DC converter modules.

While this has enabled a degree of interchangeability, there has never been consensus on implementation of all of the electrical functions. And this is particularly the case for digital power, which adds another layer of complexity to the challenge of ensuring compatibility between solutions.
On top of which, the development of the PMBus standard, an open standard for communications with a protocol dedicated to power subsystem management, further complicates matters.
However, all of this brings us to the set up last year of the Architects of Modern Power (AMP) Consortium, which makes a significant step in driving forward the adoption of digital power technology. Ericsson Power Modules and its co-founders CUI and Murata of the AMP Group envisage that this initiative will go far beyond the ambitions, and certainly the achievements, of previously established trade associations within the power industry.

The goal of the alliance is to realize the most technically advanced end-to-end solutions and provide a complete ecosystem of hardware, software and support. More specifically, the AMP Group will work on standards for mechanical specifications, monitoring, control and communications functions, as well as the creation of common configuration files that will ensure compatibility between each company’s products.
And in fact, the first standards have already been defined, and announced at Electronica 2014, by the AMP Group for digital POL converters. These new first standards detail mechanical footprints, electrical features and configuration files.
Working together in close cooperation, the three founding companies of the AMP Group can achieve far more than one acting alone: they can pool R&D resources, share a long-term strategic roadmap, and bring to bear high levels of collaborative effort in the development of leading-edge digital power technology.

Ericsson Power Modules
www.ericsson.com/powermodules
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The lifecycle of an idea

In May last year, one of just 200 Apple I computers ever made sold at auction in Germany for more than £400,000. Apple co-founder Steve Wozniak designed and hand-built the first machine immediately after going to a meeting of the Homebrew Computer Club in a Menlo Park, California garage.



Author: Steve Vecchialrelli, Vice President Supply Chain Solutions, Digi-Key

Two years later, Apple launched its first volume-sales machine, the Apple II, which was a more advanced and carefully cost-optimised design. To help with customer support, as Wozniak was the only person with first-hand knowledge of the inner workings of the original, the company offered trade-in deals to encourage customers to move to the more advanced machine. It was a recognition of the many factors at play in the construction of an electronic system – the importance of ongoing support in a product’s lifecycle.
To ensure that the launch and ongoing support of a product is as smooth and successful as possible, many functions – and often a variety of people – will be involved throughout the lifecycle. As well as design engineering, marketing, product planning, purchasing and supply management, field support, reliability engineering, production engineering, quality and even key customers will play roles in the development lifecycle. Historically, many of these functions would have been performed serially.
The lifecycle might start with the familiar “back of an envelope” sketch, quickly moving on to a proof-of-concept design. This version would not be expected to go into production. Instead, it would go through a series of revisions that focus on improving production cost, reliability and usability. Purchasing and supply-chain management plays a key role in this process by focusing not just on component pricing but continuity of supply.
In recent years, many electronics OEMs have embarked on a programme of supplier consolidation, in which they favour a small number of larger suppliers with which they can negotiate better pricing and ensure that all the components they require are available even in times of shortage. This can involve significant redesign to a proof-of-concept version to ensure that components selected by the engineering team fit the purchasing policy or that a waiver has been organised for key parts. Similarly, marketing and sales play key roles in product planning as they have the information available to them on how much they can charge and make reasonable predictions on sales levels assuming the system meets its objectives. If a product is too expensive, it will need to be redesigned to reduce its cost or have its functionality expanded to fit into a higher price bracket.
With information on expected sales, marketing can help purchasing negotiate volume discounts.
Although the various product planning and re-engineering functions can be performed serially, in today’s fast-moving marketplace, it is unlikely to be successful. The entire lifecycle of a product can be just two or three years, from idea to end-of-life. Decisions taken early will have a dramatic effect on the product’s success.
OEMs have to be able to move from design to full production extremely quickly to beat their competition. The time from prototype to production needs to be extremely short and rules out the process of serial redesigns. As a result, design engineering as a function is being tightly integrated with purchasing, marketing and other engineering roles.
Engineers now start out with approved lists of suppliers and perform cost analyses to provide marketing with early guidance on likely end-user pricing levels. This is a laborious process without tools. To support the engineer in making decisions guided by supply-chain issues we have seen the introduction of tools that help build up the bill of materials (BOM).
A BOM management tool, such as the BOM Manager software from Digi-Key, provides instant feedback on component-selection decisions and collates much of the information needed to keep other parts of the team in the loop. The software on its own is not enough. A direct link from BOM management to distribution is vital, because this provides all-important feedback on how easy it will be to source components from prototype to production.
Stocked product at a major catalogue distributor is an important indicator of the ease with which product can be sourced throughout its lifecycle. These are generally products with a large customer base or the prospect of one, which in itself provides high assurance of supply needs being met later on. By selecting stocked product, design engineers can also be sure of receiving parts for the prototype as quickly as possible – within 48 hours with a major distributor. By selecting the distributor with the greatest breadth of BOM, the design engineering team can more easily meet deadlines while selecting components from the supplier list approved by purchasing.
As well as providing feedback on stocking and pricing levels, a sophisticated BOM management tool can inform component selection over the entire lifecycle of a product idea. Because it is tied into the distribution network, it can determine whether a given component is coming to the end of its own lifecycle. If a component is not recommended for new designs, that will be shown in the tool.
The BOM management tool can provide vital information to the marketing team by allowing what-if analyses of volume purchases. For example, the engineers can quickly determine how per-part component prices will shift as the end product moves into higher volume. At the same time, the BOM management tool will determine the most effective means of packaging for each product. For prototype and early production runs, it will, for example, select cut-tape packaging for components in favour of full reels. The result of these features is a highly effective tool that minimises the amount of rework needed to get from the initial concept and prototype to production.
BOM management in partnership with the supply information that only a leading distributor can provide are becoming essential tools not only in shortening the time from prototype to production but in supporting the entire lifecycle of an idea.

Digi-Key Corporation
www.digikey.com
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Aurocon COMPEC offers a wide range of microcontrollers

Analog Devices Evaluation Board ADSP-CM408F Cortex-M4


This Mixed-Signal Control Processor integrates dual high precision 16 bit ADCs and an ARM® Cortex-M4TM processor core with floating-point unit operating at 240 MHz core clock
frequency. It also integrates 384KB of SRAM memory, 2M byte of flash memory and accelerators and peripherals optimised for motor control, photo-voltaic (PV) inverter control and other embedded control applications.

• DSP-CM408F mixed-signal control processor
• Two 16-bit ADCs with 8 inputs each
• 10/100 Ethernet PHY
• 40 character TWI display interface
• Expansion Interface

RS stock no.: 798-9711

Beaglebone Black Rev C


This low-cost, community-supported development platform for developers and hobbyists
features 4GB of built-in storage. The eMMC storage is faster, and the move to double the amount of included storage will allow the developers to make another change: The Rev C board will ship with Debian Linux instead of Angstrom Linux.

• Processor: Sitara AM3358BZCZ100 1GHz ARM Cortex-A8
• Graphics engine: SGX530 3D, 20M Polygons/sec
• SDRAM memory: 512MB 800MHz DDR3L
• Flash memory: 4GB 8-bit eMMC
• Video out: HDMI 1280 × 1024 max resolution (microHDMI)

RS stock no.: 775-3805

Texas Instruments TMS320C6748 DSP Development Kit (LCDK)


The scalable platform breaks down development barriers for applications which require
embedded analytics and real-time signal processing, including biometric analytics, communications and audio. The low-cost LCDK will also speed and ease your hardware development of real-time DSP applications.

• Integrated floating-/fixed-point DSP with up to 456 MHz performance
• Software, expansion headers, schematics and application demos
• SDKs, DSP/BIOS RTOS, drivers, stacks and protocol, algorithm libraries, flash and boot utilities and StarterWare

RS stock no.: 798-3716

Atmel SAM4S-XPRO ARM Cortex M4 Development Kit


The evaluation kit is a hardware platform to evaluate the ATSAM4SD32C microcontroller.
With the Atmel Studio integrated development platform, gain easy access to the features of the Atmel ATSAM4SD32C and see how to integrate the device in a custom design. Includes an on-board Embedded Debugger and no external tools are necessary to program or debug the ATSAM4SD32C.

• ARM Cortex M4 processor microcontroller ATSAM4SD32C
• Two crystals: 12MHz,32kHz can be used as clock sources for the SAM4S device
• LCD display header and three extension headers
• 2Gb NAND Flash for non-volatile storage
• SD card connector

RS stock no.: 800-7620

Tiva™ C Series TM4C123G Launchpad Evaluation Board


The Tiva™ C Series TM4C123G LaunchPad Evaluation Kit is a low-cost evaluation
platform for ARM® Cortex™-M4F-based microcontrollers from Texas Instruments. The design
of the TM4C123G LaunchPad highlights the TM4C123GH6PM microcontroller with a USB 2.0 device interface and hibernation module.The EK-TM4C123GXL also features programmable user buttons and an RGB LED for custom applications. The stackable headers of the Tiva™ C Series TM4C123G LaunchPad BoosterPack XL Interface make it easy and simple to expand the functionality of the TM4C123G LaunchPad when interfacing to other peripherals with Texas Instruments' MCU BoosterPacks.

• TM4C123G LaunchPad Evaluation board
• On-board In-Circuit Debug Interface (ICDI)
• USB Micro-B plug to USB-A plug cable
• Preloaded RGB quickstart application
• ReadMe First quick-start guide

RS stock no.: 795-0729

PIC32MZ Embedded Connectivity Starter Kit


The PIC32MZ EC Starter Kit provides the easiest and lowest cost method to experience the high performance and advanced peripherals integrated in the PIC32MZ Embedded Connectivity
(EC) MCUs. This starter kit features a socket that can accommodate various 10/100 Ethernet transceiver (RJ-45) plug-in connectors for prototyping and development.
On-board PIC32MZ2048ECH144: 200MHz, 2MB Flash and 512KB RAM
Includes 10/100 Fast Ethernet LAN8740 PHY Daughter Board
Features Energy Efficient Ethernet (IEEE 802.3az) and Wake-On-LAN functionality

• Integrated debugger/programmer
• USB powered
• 10/100 Ethernet
• CAN 2.0b, HI-Speed USB 2.0 host / device / dual-role / OTG
• 4MB SQI Flash
• Can be used with Multimedia Expansion Board II
• Can be used with PIC32 Expansion Board using a PIC32MZ adaptor board

RS stock no.: 796-1586

Aurocon Compec
www.compec.ro
www.designspark.com


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Processor options for FPGAs

Processors and field-programmable gate arrays (FPGA) often go hand-in-hand in system design. This provides the engineer with flexibility in both software and hardware. In 2002, Xilinx brought the two closer together with the launch of the Virtex II Pro family.

Author: Tony Storey, Application Engineer, Digi-Key

Each Virtex II Pro FPGA contained not one, but two, PowerPC 400-series microprocessors implemented in hardwired logic rather than programmable gates. It was a visionary move that increased the flexibility of the FPGA by providing an efficient way to bring software into the programmable fabric. The PowerPC processor could provide the basis for building complex state machines or hosting real-time operating systems. This permitted an independent subsystem to exist within a larger design.
Today, FPGA densities are so high that a single device can be the heart of a complete embedded system. These devices easily support both the space and performance for a processor, memory and customised logic. Although a hardwired processor sitting alongside the FPGA fabric will take up less die space, many designs now put one or more processor cores into the programmable logic fabric to take advantage of its massive flexibility.
In recent years, FPGA makers have largely settled on the ARM architecture as the one to adopt for hardwired embedded processors. Microsemi was the first to bring support for the ARM architecture to the FPGA successfully. The company’s SmartFusion architecture combined the ARM Cortex-M3 with a non-volatile FPGA fabric based on flash technology.
This allows the hardware-based parts of the system to be active as soon as power is restored, rather than having to wait for the FPGA configuration from external ROM.
The higher-performance Cortex-A9 forms the heart of two major families of FPGAs launched recently by Altera and Xilinx. In both the Altera Cyclone SoC and Xilinx Zynq devices there are two ARM processors, allowing the devices to be used as high-performance compute engines.
As well as bringing the Cortex-M3 to the FPGA market, Microsemi was instrumental in introducing an ARM M-series MCU version for use in standard programmable logic. Optimised for implementation within an FPGA’s programmable fabric, the Cortex-M1 is a streamlined version of the Cortex-M3. The Cortex M1 is designed to not require much more die space than an 8051 core, despite being based on a 32-bit pipeline rather than 8-bit. Like the M3, the M1 runs the Thumb2 instruction set, but with some instructions and features removed. The M1 interrupt structure was simplified to save space; it supports 32 interrupt sources versus the M3’s 256.
The availability of open-source development tools has helped bring other architecture cores into FPGAs. Altera, Lattice and Xilinx each have their own RISC-like processor architectures. Each has been optimised for use within the programmable logic fabric. By bringing their compilation and linking tools into free environments such as Eclipse, the FPGA vendors make it easier for developers to switch from a standard architecture to their own.
Licensing considerations may influence which core and FPGA a designer may wish to use when the design goal is to go to a standard cell ASIC. Some soft MCUs are only licensed for use with a given FPGA supplier’s devices. This limits the ability of the designer to migrate a design to an ASIC. The advantage of these MCU cores is that they have a fully supported design and implementation flow; this makes inserting IP and subsequent development remarkably easy.
The LatticeMico32 has a more flexible licensing arrangement, which has helped to foster the architecture’s use with advocates of open-source hardware. Lattice allows the processor to be used in designs that may be migrated to ASICs supplied through independent foundries or even other FPGA architectures.
Designers need not be limited to vendor-supplied soft-processor cores. Based on the Sparc architecture originally developed by Sun Microsystems, now part of Oracle, the Leon family of cores and the OpenRISC 1200 are open-source IP blocks from independent sources. The cores typically take up more die space than LatticeMico32, Microblaze or Nios – typically 1.5 to 2 times larger in terms of logic elements used in an architecture that uses conventional four-input lookup tables – but provide flexible alternatives to the vendor-supplied cores.
As well as off-the-shelf cores, the programmable nature of the FPGA provides the designer with an excellent opportunity to build custom processors. The Cyclone SoC and Zynq architectures were developed specifically with this use in mind – devices in both families have wide I/O buses to transfer bulk data between the programmable-logic sections and the processor.

Over the years, FPGA suppliers have added support for high-speed computation, particularly for signal-processing applications.
Multipliers can consume a lot of area in a standard architecture based on lookup-table elements. The most efficient way to implement multiplication in programmable cells is to use bit-serial arithmetic. The multipliers are slow because they work by adding and shifting one bit at a time. Bit-serial multipliers excel when used in massively parallel arrays, they can support high aggregate data-rates.
The simplicity and compact nature of the bit-serial multiplier makes it possible to use many of them in a single FPGA. If latency is not important, they still make a good choice.
To speed up processing, FPGA vendors added carry-chain logic to let designers implement faster carry-lookahead and carry-save adders in programmable logic. Many FPGA architectures, including cost-optimised products such as the Altera Cyclone and Xilinx Spartan-6, now include hardware multiplier blocks for use in high-speed DSP applications.
These blocks can be quite narrow to reduce their die consumption but they can easily be tied together to form more sophisticated 32-bit and 64-bit multipliers, using programmable logic cells to add support for more sophisticated features such as floating-point arithmetic. Some architectures provide a variety of DSP cores to suit target applications. These cores contain multiple narrower 9-bit units favoured for image and video processing and wider cores used for audio and communications signals.
Thanks to the programmable nature of the FPGA fabric, it is possible to build coprocessors that adapt to the needs of the system. Partial reconfiguration can allow different coprocessor blocks to be loaded into the fabric, executed and then replaced with another algorithm. For example, in an audio processing algorithm, the FPGA fabric may perform spectral processing using fast Fourier transforms (FFT) followed by filtering using a finite impulse response (FIR) filter loaded into the same section once the spectral analysis has completed.
The programmability of the fabric also helps to streamline data flow through a coprocessor element. In the case of an FFT, implementations of the algorithm in a general-purpose processor are often relatively slow because the ‘butterfly’ data-access pattern the algorithm requires involve repeated fetching and writing of temporary values in cache or main memory – the latency of those accesses may mean the internal arithmetic-logic units are starved of data. The FPGA fabric makes it possible to insert those temporary values into a complex pipeline structure that ensures DSP elements are fed with relevant data at all times.
The FPGA fabric provides advantages for operations that do not fit easily into standard ALUs. For example, cryptographic functions and many algorithms used in digital communications, such as Viterbi and Turbo decoders, often make use of modulo and other non-standard arithmetic.
With full control over the logic elements, an FGPA-based custom ALU will almost always outperform a software emulation running on a standard processor core.
The arrival of languages such as OpenCL is likely to ease the construction of coprocessor elements that can be laid out and torn up as required. Although OpenCL was developed originally to make the compute power of graphics processing units (GPUs) available to programmers more accustomed to working with general-purpose architectures such as ARM or the x86, companies such as Altera have embraced OpenCL as a way of making it easier to build custom compute engines.
OpenCL functions take the form of compute kernels – tight vector-fashioned loops that can be used to process multiple data elements in parallel. OpenCL comprises a runtime environment that loads kernels and respective data into target processors, starting execution and then fetching results once completed. Compilation tools take care of converting the algorithm expressed in the OpenCL language into an implementation suitable for configuration within an FPGA.
Another way to offload software overhead from the processor inside an FPGA is to reduce the frequency of interrupts. Each interrupt demands the processor stop whatever it is doing in order to capture or send a fragment of data through an I/O port, each interrupt involves pushing and register contents onto the stack occupying processor cycles. The analogue compute engine (ACE) in Microsemi’s SmartFusion is a small independent parallel processor that controls the various analogue I/O ports supported by the device.
The ACE combines a sample sequencing engine (SSE) with a post-processing engine (PPE). The SSE captures data from the analogue inputs, passing it to the PPE which can perform functions such as low-pass filtering, to remove noise, and transform the data into a format convenient for the processor. Devolving these functions into hardware ensures they can be used to greatly reduce the interrupt burden on the processor.
Similar techniques can, naturally, be implemented in FPGAs that lack these features to reduce the interrupt load for other processor cores. With an FPGA, there are always many ways to bring software processing and parallelised hardware speed together.

Digi-Key Corporation
www.digikey.com
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The fundamental components of the Internet of Things


Figure 1: Comparing data rates of RF systems.

The focus of the internet is set to change over the next five years as systems become smarter. According to networking specialist Cisco, 50 billion devices are likely to be connected to the internet by 2020, helping to sustain a $14tr market. The systems that dominate the internet today, such as PCs, laptops, tablets and smartphones, will be dwarfed by the tens of billions of machines with network connections that will relay data to each other with the aim of making life more efficient.
The idea of the internet of things (IoT) dates back to the late 1990s when researchers proposed ideas such as ambient intelligence, in which a forest of smart sensors would monitor environmental conditions, alerting control systems to changes. By enacting changes in response, these control systems can improve efficiency in a wide range of systems, from industrial control through home automation to healthcare. For example, a set of smart sensors dotted around the body, can pick up on health problems that alert the user to a problem through their phone.



Author: Mark Zack, VP Global Semiconductors, Digi-Key

In industrial control, a series of sensors mounted along a production line can detect conditions that may lead to problems such as sudden changes in temperature or excess vibration that may signal a problem in a machine tool or a process going outside its bounds.
There are three fundamental components that combine to form an IoT node: intelligence, sensing, and wireless communications. Wireless connectivity is vital because it will allow sensor nodes to be deployed quickly and easily without the requirement to route network cables to each location.
In order to survive for long periods of time on a single battery charge, an IoT node needs to exhibit low power consumption. Typically, the node will be dormant for long periods of time, waking up for short periods to take a reading and then make a decision on whether to send out an alert based on the change or go back to sleep. A large number of microcontrollers are designed around this core requirement, sporting ultralow-energy sleep modes combined with high-performance instruction pipelines to streamline processing while awake.
A key decision is the type of architecture. A growing number of low-cost microcontrollers from vendors such as Atmel, Freescale, STMicroelectronics and Texas Instruments use 32-bit cores based on architectures such as ARM to deliver high performance at low power and access to a growing range of open-source software that allows applications to be built quickly. However, architectures such as Atmel’s AVR demonstrate that the 8-bit platform still provides a great deal of power, using advanced smart peripherals to collect data from sensor interfaces, and delivering high cost-effectiveness.
There are a number of possible approaches for introducing low-power communications to an IoT node, ranging from purpose-designed protocols such as Zigbee to low-power variants of Bluetooth and Wi-Fi. Some of these protocols offer direct compatibility with the internet protocol (IP). Others rely on a gateway to map between IP packets and the leaner protocols used by the IoT sensor nodes.

Zigbee is a low-power wireless network specification based on the IEEE 802.15.4 (2003) standard that was developed by a group of 16 companies involved in industrial and building automation. A novel aspect of Zigbee compared to many other networking protocols lies in its use of mesh networking. This allows IoT nodes far away from a central controller to use nodes in between to carry their communications. This not only extends the range of a central gateway, it also increases robustness as a transmission can use a number of different routes through the mesh.

Originally launched by Nokia as Wibree in 2006, Bluetooth Low-Energy (BLE) or Bluetooth Smart provides a similar range to classic Bluetooth but with reduced power consumption. In place of the 1MHz channels used by the original Bluetooth protocol, BLE uses a smaller set of wider-bandwidth channels of 2MHz but with a lower peak data rate.
The channel bandwidth is similar to that of Zigbee but with narrower spacing.
A key advantage of BLE is its lower latency, just 3ms versus the 100ms of classic Bluetooth, as well as lower complexity so that its software stack can easily be incorporated into lower-cost microcontrollers. BLE retains support for frequency hopping from the original Bluetooth protocol, which makes it more robust than Zigbee in the presence of strong interfering signals.

Figure 2: Channel arrangements for Zigbee, BluetoothLE and Wi-Fi.
One of the main application areas for BLE is medical instrumentation, where a number of on-body sensors to monitor heart rate, blood pressure, and posture relay their readings at regular intervals to a central controller, which may be a mobile phone or a dedicated medical instrument.
Having been in use in various forms for more than 15 years, Wi-Fi has the benefit of being the most mature wireless-networking radio technology suitable for IoT applications. Through protocols such as WPS, Wi-Fi can offer easy integration into an existing network for devices that have little to no physical user interface.
Of the wireless technologies suitable for IoT applications, Wi-Fi has the best power-per-bit transmission efficiency. Conventional Wi-Fi designs tend to use more energy to maintain a connection while quiescent than protocols such as BLE, which can decrease energy efficiency if the application does not need high bandwidth. However, vendors such as GainSpan have worked on power efficiency in designs such as the GS2000, which combines support for both ZigBee and Wi-Fi on the 2.4Ghz and 5GHz band. These designs put the radio into an energy-saving standby mode if the sensor node does not need to transmit any data. It wakes up only to send data or keep-alive connection packets used to assure central controllers that the node has not failed.
In general, Wi-Fi tends to suit applications where compliance with the IP stack is an advantage, there is a requirement to deliver large amounts of data, such as audio or video, or the remote devices can be powered by external energy sources.

An example of Wi-Fi in use is by Mernok Elektronik of South Africa, which used modules from connectBlue to incorporate wireless networking into the locomotive control and safety management systems of railway systems used in mining.
The modules are used to collect real-time operation data on each vehicle and provide a robust wireless connection across both 2.4GHz and 5GHz frequency bands with support for over-the-air firmware updates and parameter changes.

BLE and Wi-Fi can be used together efficiently as they both support coexistence protocols designed to reduce interference between the two on their common frequency band of 2.4GHz. This coexistence ability lends itself to implementation in gateway designs where BLE is used for connections to sensor nodes and Wi-Fi for relaying aggregated data to a backbone network.
The APx4 from Bluegiga provides an off-the-shelf solution for this, providing support for both Wi-Fi and the full Bluetooth 4.0 software stack that includes BLE, based around a powerful 450MHz ARM9 processor.
A number of integrated microcontrollers and support chipsets from vendors such as Atmel, CSR, Freescale, STMicroelectronics and Texas Instruments provide support for protocols such as BLE, Wi-Fi and ZigBee. For implementations that need flexibility, the configurable radio transceivers made by Lime Microsystems make it easier to deploy nodes that can be programmed with a specific RF interface personality at the point of manufacture to suit different networking needs in the target system.
As the IoT scales up, we can expect more integrated solutions to arrive on the market. But, even at this early stage of development, there are many choices available to the engineer with which to incorporate the three key components of IoT support.

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