Latest news

Secure NFC/RFID Tag Authenticator

Maxim Integrated’s MAX66242 DeepCover® Secure Authenticator authenticates, configures, and collects data from any embedded system through its NFC/RFID wireless data communication and simple I2C interfaces.
Designers can now perform secure wireless data communication on their embedded systems without needing the host microcontroller, but by simply using a single MAX66242 DeepCover® Secure Authenticator from Maxim Integrated Products, Inc.
The MAX66242 secure authenticator is an advanced tag that combines a wireless NFC/RFID interface with an I²C ... Read more Read more

Face recognition goes embedded with Omron Vision Module

Face and gesture recognition functionality can be added to any embedded system for medical, industrial control, digital advertising, security and other applications, following the launch by Omron Electronic Components Europe of a Human Vision Component (HVC) module. The module handles all the complexity of seeing and recognising faces,

Face and gesture recognition functionality can be added to any embedded system for medical, industrial control, digital advertising, security and other applications, following the launch by Omron of a Human Vision Component (HVC) module. Source: Omron Electronic Components.
bodies and gestures, all the integrator needs to do is read the data output and programme the system to react appropriately.

The new Omron HVC integrates ten key image sensing functions with a camera in a module sized just 60 × 40mm. Developers can detect a human face, hand or body, and implement face recognition, gender detection, age estimation, mood estimation, facial pose estimation, gaze estimation, and blink estimation. In each case the module returns a value together with a degree of certainty, allowing the programmer to configure the response appropriately for each individual application. HVC is designed in a very compact configuration and can be easily integrated into an established system or implemented as part of a new design.

Commenting, Gabriel Sikorjak, European Product Marketing Manager at Omron Electronic Components, said, “Face recognition and gesture control have been features of high volume consumer electronics for some time. Omron’s new module gives any embedded system developer access to this technology, without needing any understanding of the complexities of the underlying algorithms or the optical design. The module is a fully integrated, plug-in solution. The developer can just look at the outputs and configure the system to make appropriate decisions depending on their status.”
The module is based on the Omron OKAO Vision software, a proven set of image recognition algorithms used in over 500 million digital cameras, mobile phones and surveillance robots around the world. HVC embeds OKAO on a hardware platform optimised specifically in terms of its digital and optical design for this application. HVC includes a camera and a processor, and a UART interface to control the module and read data.

Face and gesture recognition functionality can be added to any embedded system for medical, industrial control, digital advertising, security and other applications, following the launch by Omron of a Human Vision Component (HVC) module. Source: Omron Electronic Components.
Key features of the module include speed and consistency of response, and the distance over which it can take readings. For example, HVC can capture, detect and recognise a face over a distance of 1.3 m in 1.1s and will provide a confidence level with its reading. Blink and gaze estimation takes under 1s.
The module can evaluate the subject’s mood based on one of five expressions. It can also detect a human body up to 2.8m away and a hand at a distance of 1.5 m. The detection angle of the module is specified as 49° horizontally and 37° vertically.

Image analysis functions provided by HVC can enable smoother interaction between people and machines, and optimise equipment reaction under various conditions in indoor and outdoor applications. Omron is also offering the OKAO vision software separately to developers who prefer to implement their own hardware solution.

Omron Electronic Components Europe
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The lifecycle of an idea

In May last year, one of just 200 Apple I computers ever made sold at auction in Germany for more than £400,000. Apple co-founder Steve Wozniak designed and hand-built the first machine immediately after going to a meeting of the Homebrew Computer Club in a Menlo Park, California garage.

Author: Steve Vecchialrelli, Vice President Supply Chain Solutions, Digi-Key

Two years later, Apple launched its first volume-sales machine, the Apple II, which was a more advanced and carefully cost-optimised design. To help with customer support, as Wozniak was the only person with first-hand knowledge of the inner workings of the original, the company offered trade-in deals to encourage customers to move to the more advanced machine. It was a recognition of the many factors at play in the construction of an electronic system – the importance of ongoing support in a product’s lifecycle.
To ensure that the launch and ongoing support of a product is as smooth and successful as possible, many functions – and often a variety of people – will be involved throughout the lifecycle. As well as design engineering, marketing, product planning, purchasing and supply management, field support, reliability engineering, production engineering, quality and even key customers will play roles in the development lifecycle. Historically, many of these functions would have been performed serially.
The lifecycle might start with the familiar “back of an envelope” sketch, quickly moving on to a proof-of-concept design. This version would not be expected to go into production. Instead, it would go through a series of revisions that focus on improving production cost, reliability and usability. Purchasing and supply-chain management plays a key role in this process by focusing not just on component pricing but continuity of supply.
In recent years, many electronics OEMs have embarked on a programme of supplier consolidation, in which they favour a small number of larger suppliers with which they can negotiate better pricing and ensure that all the components they require are available even in times of shortage. This can involve significant redesign to a proof-of-concept version to ensure that components selected by the engineering team fit the purchasing policy or that a waiver has been organised for key parts. Similarly, marketing and sales play key roles in product planning as they have the information available to them on how much they can charge and make reasonable predictions on sales levels assuming the system meets its objectives. If a product is too expensive, it will need to be redesigned to reduce its cost or have its functionality expanded to fit into a higher price bracket.
With information on expected sales, marketing can help purchasing negotiate volume discounts.
Although the various product planning and re-engineering functions can be performed serially, in today’s fast-moving marketplace, it is unlikely to be successful. The entire lifecycle of a product can be just two or three years, from idea to end-of-life. Decisions taken early will have a dramatic effect on the product’s success.
OEMs have to be able to move from design to full production extremely quickly to beat their competition. The time from prototype to production needs to be extremely short and rules out the process of serial redesigns. As a result, design engineering as a function is being tightly integrated with purchasing, marketing and other engineering roles.
Engineers now start out with approved lists of suppliers and perform cost analyses to provide marketing with early guidance on likely end-user pricing levels. This is a laborious process without tools. To support the engineer in making decisions guided by supply-chain issues we have seen the introduction of tools that help build up the bill of materials (BOM).
A BOM management tool, such as the BOM Manager software from Digi-Key, provides instant feedback on component-selection decisions and collates much of the information needed to keep other parts of the team in the loop. The software on its own is not enough. A direct link from BOM management to distribution is vital, because this provides all-important feedback on how easy it will be to source components from prototype to production.
Stocked product at a major catalogue distributor is an important indicator of the ease with which product can be sourced throughout its lifecycle. These are generally products with a large customer base or the prospect of one, which in itself provides high assurance of supply needs being met later on. By selecting stocked product, design engineers can also be sure of receiving parts for the prototype as quickly as possible – within 48 hours with a major distributor. By selecting the distributor with the greatest breadth of BOM, the design engineering team can more easily meet deadlines while selecting components from the supplier list approved by purchasing.
As well as providing feedback on stocking and pricing levels, a sophisticated BOM management tool can inform component selection over the entire lifecycle of a product idea. Because it is tied into the distribution network, it can determine whether a given component is coming to the end of its own lifecycle. If a component is not recommended for new designs, that will be shown in the tool.
The BOM management tool can provide vital information to the marketing team by allowing what-if analyses of volume purchases. For example, the engineers can quickly determine how per-part component prices will shift as the end product moves into higher volume. At the same time, the BOM management tool will determine the most effective means of packaging for each product. For prototype and early production runs, it will, for example, select cut-tape packaging for components in favour of full reels. The result of these features is a highly effective tool that minimises the amount of rework needed to get from the initial concept and prototype to production.
BOM management in partnership with the supply information that only a leading distributor can provide are becoming essential tools not only in shortening the time from prototype to production but in supporting the entire lifecycle of an idea.

Digi-Key Corporation
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Remember Dr. Who’s Tardis time travel machine?

The British sci-fi television show, Dr. Who, used a Tardis to move around space and time. The Tardis looked like a police box on the outside, but the inside was huge with tons of rooms and equipment. How did the Tardis do this? It presumably exploited extra dimensions in space time to step out of our 3D world into new dimensions, providing plenty of room inside the police box and the opportunity to sustain decades of new storylines and a worldwide cult following.

Author: Sam Fuller, Head of System Solutions, Freescale Semiconductor

What has this got to do with networking equipment?

The Tardis, while physically a small box, provides a gateway into other dimensions. In a similar fashion, the combination of software-defined networking (SDN) and network function virtualization (NFV) provide mechanisms to extend the processing capabilities of a networking gateway well beyond the capabilities of the processor that is contained in the gateway box. The result is a cyberspace equivalent of a Tardis. This is important because next-generation networking equipment is challenged with both significantly higher bandwidth requirements (Gigabit to the home is a reality in many places now), but also the need for more network service processing such as firewalls, content filters and traffic shaping. These new services can provide more revenue to service providers and value to customers.

How do SDN and NFV allow for this to happen?

SDN and NFV are two different technologies. They are designed to solve different problems in networking, but they are quite complementary when used together.

• SDN separates the control plane and the data plane of networking equipment and allows the control plane to be centralized such that a single controller can manage many data forwarding elements.
• NFV is a technique to implement networking functions as virtual appliances running on general purpose processors.
• SDN deals with the way networks are controlled and managed, while NFV provides a new approach to implementing network functions such as routing, firewalling and even switching.

In traditional networking, customer premise equipment combines a local LAN switch and a routing function. These two functions operate independently – a bridging/switching function to locally switch packets at the Layer 2 level and a routing function to forward the packets to WAN (Wide Area Network) at the Layer 3 level. Network elements’ bridging and routing functions operate based on the Ethernet MAC addresses and IP addresses of the packets. In the SDN paradigm these two separate functions are combined into a single flow forwarding function. Each flow path can be controlled independently with no special considerations to MAC addresses and IP addresses of the packets. Additionally each flow can be programmed with various actions independently. This flow level fine grain granular control is one of the unique properties of SDN.
For example, an email flow can be applied with various actions that take the packets across network services such as IPS, firewall, anti-malware and antispam, whereas HTTP flow can be applied with various actions that take the packets through firewall, anti-malware and content filtering. Other examples include applying various QoS parameters based on the application to which the flow belongs to. Essentially, in an SDN paradigm, flow properties and flow paths can be controlled from a different place instead of making local decisions, thereby providing an opportunity to control the customer premise equipment (CPE) devices by service providers remotely.
As discussed above, SDN-based CPE is designed to allow the CPE to be controlled remotely, on a per flow basis. Typically CPEs are implemented using multicore processors and discrete switching and modem ASICs. While the modem functionality will typically remain separate, for many applications the switch and the multicore processor can be integrated onto a single piece of silicon. In fact, because of the performance of multicore processors such as QorIQ platform from Freescale, the SDN flow forwarding function for CPE can be implemented in software for the most common CPE equipment with network uplink connectivity between 100 Mbps and 10 Gbps.
With an SDN-enabled CPE, secure channels can be provided that extend the processing capabilities of the CPE back to the software running on an aggregated network processing infrastructure, thereby enabling the addition of value added network services such as firewalls, deep packet inspection, content filtering, antimalware and more. The key insight is realizing that packet processing associated with a logical piece of network equipment does not need to occur within the single box located at the customer’s premise. Rather, it can be divided between work occurring on the CPE and work occurring in the cloud or PoP (Point of Presence) location. The growth in backhaul bandwidth and low latency networks makes this possible and the SDN and NFV paradigms provide a common scalable approach to providing these new capabilities.
Designers of networking equipment can now open their horizons significantly in terms of how they provide the functions their customers demand. Cloud-based processing can reduce cost and allow all sorts of new services that were inconceivable based on traditional networking technologies.
Like the Tardis on Dr. Who, with its ability to transcend the limits of three dimensional space, the combination of SDN and NFV in next-generation networks provide new mechanisms to enable network services and capabilities that extend and expand well beyond what a traditional gateway box working alone could provide.
Freescale recognized the shift to SDN very early on and has made significant hardware and software investments to support it. Freescale is committed to providing high-performance multicore processors and software solutions required to build SDN-based networking environments. Our product and development teams operate under the fundamental belief that SDN changes the way that processors are designed, enabled and supported and we have placed a strong emphasis on architecting our solutions to to meet the needs of next-generation networks.
Visit to learn more. And, check out the new informative video on SDN ( ).

Sam Fuller is the Head of System Solutions for the Digital Networking Group at Freescale Semiconductor. Mr. Fuller has over 20 years of executive leadership experience in computer architecture, SoC architecture, embedded systems and semiconductor marketing and applications, and has led innovative development efforts in SIMD processing, fabric interconnects and symmetric multicore processing. Mr. Fuller holds BSEE and MSEE degrees from Brigham Young University and an MBA degree from the University of Texas at Austin.
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Aurocon COMPEC offers a wide range of microcontrollers

Analog Devices Evaluation Board ADSP-CM408F Cortex-M4

This Mixed-Signal Control Processor integrates dual high precision 16 bit ADCs and an ARM® Cortex-M4TM processor core with floating-point unit operating at 240 MHz core clock
frequency. It also integrates 384KB of SRAM memory, 2M byte of flash memory and accelerators and peripherals optimised for motor control, photo-voltaic (PV) inverter control and other embedded control applications.

• DSP-CM408F mixed-signal control processor
• Two 16-bit ADCs with 8 inputs each
• 10/100 Ethernet PHY
• 40 character TWI display interface
• Expansion Interface

RS stock no.: 798-9711

Beaglebone Black Rev C

This low-cost, community-supported development platform for developers and hobbyists
features 4GB of built-in storage. The eMMC storage is faster, and the move to double the amount of included storage will allow the developers to make another change: The Rev C board will ship with Debian Linux instead of Angstrom Linux.

• Processor: Sitara AM3358BZCZ100 1GHz ARM Cortex-A8
• Graphics engine: SGX530 3D, 20M Polygons/sec
• SDRAM memory: 512MB 800MHz DDR3L
• Flash memory: 4GB 8-bit eMMC
• Video out: HDMI 1280 × 1024 max resolution (microHDMI)

RS stock no.: 775-3805

Texas Instruments TMS320C6748 DSP Development Kit (LCDK)

The scalable platform breaks down development barriers for applications which require
embedded analytics and real-time signal processing, including biometric analytics, communications and audio. The low-cost LCDK will also speed and ease your hardware development of real-time DSP applications.

• Integrated floating-/fixed-point DSP with up to 456 MHz performance
• Software, expansion headers, schematics and application demos
• SDKs, DSP/BIOS RTOS, drivers, stacks and protocol, algorithm libraries, flash and boot utilities and StarterWare

RS stock no.: 798-3716

Atmel SAM4S-XPRO ARM Cortex M4 Development Kit

The evaluation kit is a hardware platform to evaluate the ATSAM4SD32C microcontroller.
With the Atmel Studio integrated development platform, gain easy access to the features of the Atmel ATSAM4SD32C and see how to integrate the device in a custom design. Includes an on-board Embedded Debugger and no external tools are necessary to program or debug the ATSAM4SD32C.

• ARM Cortex M4 processor microcontroller ATSAM4SD32C
• Two crystals: 12MHz,32kHz can be used as clock sources for the SAM4S device
• LCD display header and three extension headers
• 2Gb NAND Flash for non-volatile storage
• SD card connector

RS stock no.: 800-7620

Tiva™ C Series TM4C123G Launchpad Evaluation Board

The Tiva™ C Series TM4C123G LaunchPad Evaluation Kit is a low-cost evaluation
platform for ARM® Cortex™-M4F-based microcontrollers from Texas Instruments. The design
of the TM4C123G LaunchPad highlights the TM4C123GH6PM microcontroller with a USB 2.0 device interface and hibernation module.The EK-TM4C123GXL also features programmable user buttons and an RGB LED for custom applications. The stackable headers of the Tiva™ C Series TM4C123G LaunchPad BoosterPack XL Interface make it easy and simple to expand the functionality of the TM4C123G LaunchPad when interfacing to other peripherals with Texas Instruments' MCU BoosterPacks.

• TM4C123G LaunchPad Evaluation board
• On-board In-Circuit Debug Interface (ICDI)
• USB Micro-B plug to USB-A plug cable
• Preloaded RGB quickstart application
• ReadMe First quick-start guide

RS stock no.: 795-0729

PIC32MZ Embedded Connectivity Starter Kit

The PIC32MZ EC Starter Kit provides the easiest and lowest cost method to experience the high performance and advanced peripherals integrated in the PIC32MZ Embedded Connectivity
(EC) MCUs. This starter kit features a socket that can accommodate various 10/100 Ethernet transceiver (RJ-45) plug-in connectors for prototyping and development.
On-board PIC32MZ2048ECH144: 200MHz, 2MB Flash and 512KB RAM
Includes 10/100 Fast Ethernet LAN8740 PHY Daughter Board
Features Energy Efficient Ethernet (IEEE 802.3az) and Wake-On-LAN functionality

• Integrated debugger/programmer
• USB powered
• 10/100 Ethernet
• CAN 2.0b, HI-Speed USB 2.0 host / device / dual-role / OTG
• 4MB SQI Flash
• Can be used with Multimedia Expansion Board II
• Can be used with PIC32 Expansion Board using a PIC32MZ adaptor board

RS stock no.: 796-1586

Aurocon Compec

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Advanced digital control increases energy efficiency in mid- to high-power applications

A reference design is proposed by Alex Dumais of Microchip Technology Inc.

The combination of the flexibility of digital power control, with the improved efficiency of Inductor, Inductor, Capacitor (LLC) resonant converters, can help telecoms and other medium to high power applications to minimise energy consumption and cooling equipment operating costs.
Digital control offers significant design advantages such as a high level of flexibility coupled with high performance and high reliability, whilst LLC resonant converters increase efficiency by significantly reducing the power dissipated by the MOSFETs within a DC-DC converter.
Together, these technologies can help companies to meet the new efficiency targets set by initiatives such as the ENERGY STAR Data Center Energy Efficiency Initiative and the 80 PLUS® Initiative. The ENERGY STAR Data Center Energy Efficiency Initiative targets information technology (IT) equipment and infrastructure, uninterruptible power supplies (UPS) and other equipment which are responsible for high levels of energy consumption.

Figure 1: Resonant tank circuit options
The 80 PLUS® Initiative addresses the fact that many power supplies time operate spend considerable time operating at loads which are far below the level at which that achieve the greatest efficiency. This initiative stipulates that 80% efficiency should be the minimum for a 115V power supply operating at 20%, 50% and 100% of its rated load. Platinum, Gold, Silver and Bronze ratings can be awarded when a supply exceeds these efficiency targets. In order to achieve the Bronze rating, for example, a 230V supply should achieve 81% efficiency at 20% and 100% of its rated load and 85% efficiency at 50% of rated load.
Further impetus for increasing power efficiency is coming from end-users who are including the requirement for power supplied to be certified by these initiatives within their purchasing contracts.
For the designer, energy-saving power-supplies can be realised by combining the efficiency of an LLC resonant converter, with the advanced digital control offered by digital signal controllers (DSCs) such as Microchip Technology’s dsPIC® family. These low pin-count DSCs offer powerful digital signal processing (DSP) capabilities in addition to intelligent power peripherals optimised digital power control.

The basics of resonant converters

Operating a converter in resonant mode, at the point where the impedance between the input and output of the circuit is at its minimum, provides improved efficiency. For example, the power dissipated by the MOSFETs in an LLC resonant converter can be significantly reduced by supplying the MOSFETs with either a sinusoidal voltage or a sinusoidal current, and switching in close proximity to the zero crossing of the sinusoidal voltage or current.

Figure 2: The quality factor (Q) affects gains from the tank circuit (M) shown on the Y axis All Q-curves intersect at the resonant frequency (fn = 1)
Switching the MOSFET when the drain-to-source voltage is near zero, Zero Voltage Switching (ZVS), and transitioning from one MOSFET state to another while the current through the switch is zero, Zero Current Switching (ZCS), minimises MOSFET switching losses. This soft-switching approach also reduces noise in the system and provides improved electromagnetic interference (EMI) performance. For high-voltage, high-power systems, ZVS would be the preferred topology.
In a resonant-switch converter, the sinusoidal voltage or current is generated by reactive elements such as capacitors and inductors. The three main classes of resonant converters are: series resonant converter (SRC), parallel resonant converter (PRC) and a combination of the two, the series-parallel resonant converter (SPRC). Figure 1 shows the high-level resonant converter block diagram and the three types of resonant-tank circuits.
In the series resonant converter, the load is connected in series with the tank’s inductor and capacitor. The gain from the resonant tank is ≤ 1. While the SRC can operate at no load, its output voltage cannot be regulated. For ZVS, the circuit needs to operate above resonance in the inductive region. At low line voltage, the SRC operates closer to resonant frequency.
In the PRC, the load is connected in parallel with the resonant capacitor. The PRC can operate at no load output and, unlike the SRC, its output voltage can be regulated at no load. For ZVS, the PRC also needs to operate above resonance in the inductive region. Similar to the SRC, at low line voltage, the PRC operates closer to resonant frequency, however, the PRC differs by having high circulating currents. The series inductor and parallel capacitor provide protection against short-circuits.
In an SPRC, the tank circuit is a combination of the series and parallel converters and can be either a LCC or LLC configuration. Similar to the SRC and PRC, a SPRC LCC design cannot be optimised at high input voltage. As a result, the preferred alternative for many applications is an LLC, shown in Figure 1.
The LLC converter can operate at resonance, at nominal input voltage, and is able to operate at no load. In addition, it can be designed to operate over a wide input voltage.
Both zero-voltage and zero-current switching are achievable over the full operating range.
The performance of a resonant converter is measured by several parameters. The quality factor (Q) of a resonant circuit is a dimensionless parameter that describes the amount of dampening in the circuit. It is defined as the ratio between the power stored and the power dissipated in the circuit. A higher Q indicates a narrower bandwidth for the resonant tank.
Quality is a key parameter in the tank circuit’s gain, which is also called the voltage conversion ratio or M. By considering the families of M curves that are generated when varying either l, the normalised frequency, or Q, it is possible to obtain an indication of a resonant converter’s performance before all the parameters have been computed.
M is defined as:

M(fsw) = f ( fn, l, Q)

fn = normalised frequency, f/fr
l = the inductance ratio, Lr/Lm
Q = quality, a function of the output

Figure 3: Digitally-controlled feedback loop for an LLC resonant converter

As shown in Figure 2, the LLC circuit for Q as a parameter has two resonant frequencies: one due to the presence of Lr and Cr, the series inductor and capacitor at 0.5; and the second one due to the parallel inductor, Lm. Lr and Cr have a resonant frequency at fn = 1 (fr) and Lm + Lr and Cr have a resonant frequency at fn ~ 0.5.
Different operating modes of the LLC include: at resonance; below resonance; or above resonance. At resonance, the MOSFETs are switched at the resonant frequency within a very narrow timing window, as determined by the selected components, to produce very low losses.
Below resonance, the circuit behaviour is similar to that at resonance, but the tank current is limited by the magnetising current for a portion of the cycle. If MOSFETs are used for synchronous rectification in the secondary instead of diodes, the gates must be turned off at the correct time. This usually requires a current-sensing technique, such as measuring the voltage drop across the MOSFETs.
Above resonance, instead of being limited by the magnetising current, the tank current is higher than the magnetising current. In this region, the synchronous switches can be turned on and off at the same time as the primary switches to simplify control.
Since zero-voltage switching is used, LLC resonant supplies have inherently low electromagnetic and radio interference.

Digital control topology for increased efficiency

Full digital control of the power-conversion and system-management functions of the LLC resonant converter can easily be implemented using the latest generations of DSCs.
In addition to the components and sections shown in Figure 1, an LLC circuit includes a DC input, switch network, LLC resonant tank, transformer, rectifier, filter and load. A digitally-controlled feedback loop for an LLC resonant converter, used in a telecoms application, is shown in Figure 3.

In telecoms, the LLC converter is widely used as the DC/DC converter following a Power Factor Correction (PFC) circuit in an AC-DC system. The typical PFC output voltage of around 400V can be directly fed into the LLC converter. The wide input range allows the use of smaller bulk capacitors. The design specifications are summarised in Table 1.
With 40 MIPS performance and intelligent power peripherals a dsPIC33FJ GS provides the digital computing power in the resonant converter. The peripherals include high-speed 16-bit PWM with features which include 1 ns period resolution and phase-shiftable outputs.

Figure 4: ZVS of the primary MOSFETs

Figure 5: Switching waveform for the synchronous rectifier
The reference design’s switching circuit uses a half-bridge topology so the half-bridge voltage swings between 0V and Vd of 400 Vdc nominal. The resonant tank circuit comprises a capacitor, inductor, and the magnetising inductance of the isolating transformer to reduce system cost by eliminating the need for an external inductor. This design can also use the transformer’s leakage inductance as the second inductor and eliminate another external inductor for additional cost savings.
If correctly tuned to the switching frequency, the resonant tank presents finite impedance to the fundamental frequency and very high impedance to all other harmonics. The impedance of the tank causes a phase shift between the voltage and current, which allows ZVS to occur. Figure 4 shows the ZVS of the primary MOSFETs.

Table 1: Specification for the telecom power supply reference design
The secondary side has been designed using a synchronous rectifier, instead of diodes, to reduce conduction losses at the secondary. This reduces both the forward resistance (Rf) and the losses due to the diode forward voltage. Figure 5 shows the switching waveform for the synchronous rectifier.
For synchronous rectification, the digital control initiates the switching of the FETs without requiring current-sensing circuitry on the secondary.
This results in improved efficiency and reduced cost over a full-wave rectifier design. Figure 6 shows the efficiency over the load current range:
The efficiency of the LLC at two different input operating voltages shows its

Figure 6: Efficiency over the load current range
insensitivity to input voltage. Over 80% efficiency is achieved with an output load current below 2A, whilst, at higher loads, the maximum efficiency is 95% and extremely flat from 7 to 17A. Additional benefits include enhanced flexibility for the compensator design, by using the DSC to implement soft-start for duty-cycle control.
Since the power-conversion control is implemented with easily reprogrammable software, it provides designers with ability to easily modify or adapt their design, or add new, cost-effective and value-creating features. The precision of the digital control also improves the power supply’s reliability.


The combined advantages of LLC resonant converters and digital control via DSCs enable designers to increase energy efficiency for DC-DC converters for telecoms and other

medium to high-power applications. Whilst LLC resonant converters can reduce power losses, digital control increases the inherent flexibility efficiency and reliability of the converter. The proposed reference provides a basis from which designers can to achieve higher efficiency converters and a faster time to market.

Microchip Technology

Further reading: A more detail description of the reference design using the dsPIC DSC is available in Microchip Technology’s AN1336 application note: DC/DC LLC

Note: The Microchip name and logo, and dsPIC, are registered trademarks of Microchip Technology Inc. in the U.S.A., and other countries. All other trademarks mentioned herein are property of their respective companies.
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Freescale offers easy way to make real development for high voltage drives

Freescale HVP-MC3PH board

The 3-phase motor has become more and more popular and has started to push out the old-fashioned 1-phase AC or DC drives. These 3-phase drives are targeted at refrigerators, washers, dishwashers, industrial drives, and almost all the moving things around us. However, the hardware in these electronic devices gets complicated and the software offers endless possibilities of functionality. Development of these devices consumes more time and requires ever more effort from the engineers. To speed up the development time and decrease the costs, Freescale has designed a cost effective high-voltage motor control development platform supporting the new ARM®-based motor control and digital power conversion Kinetis®-V family and also the Digital Signal Controller - 56F8000EX family.

Ivan Lovas and Pavel Sustek, System Application Engineers, Freescale Semiconductor
Dobrucky Branislav and Peter Cubon, University consultants, University of Zilina

I would like to offer my special thanks to Centre of Excellence of Power Electronic Systems and Materials for their Components II, No. ITMS 26220120046.

Design concept

Freescale’s high-voltage motor control platform is a new 1000 W, 3-phase power stage that will operate off DC input voltages from 110-390V, and with AC line voltages from 90-240V. In combination with one of the controller cards, it provides a software-development platform that allows algorithms to be written and tested without the designing and building of their own hardware. It supports a variety of sensorless and sensored algorithms for AC induction, PMSM and brushless DC (BLDC) motors, which can be found on the Freescale web pages
The power stage consists of the main board and interchangeable controller cards accommodating the target microcontroller.
Main board specifications:
The main board contains an input filter, input rectifier, brake switch, IPM with IGBT-gate-drive circuits, analog-signal conditioning, low-voltage power supplies and many features for easy debugging. In addition, the HV AC power stage includes an active interleaved (CCM or CRM) power factor correction (PFC) circuit that facilitates development of PFC algorithms. The main board also contains hardware over-current and overvoltage protection, temperature monitoring and galvanic isolation.

Board layout
Key Features:
• Input voltage AC: 90-240V / DC: 110-390VDC
• Output power up to 1kW
• On-board Interleaved Power Factor Correction supporting DCM, CCM, CRM
• Inrush limitation using an NTC resistor + Relay
• Optical isolation 5KV for communication and debugging
• Support communication with external devices ( for example, a Bluetooth wireless module)
• Hardware over-current, overvoltage faults
• Motor speed/position sensors interface (Encoder, Hall, Tacho generator)
• Analog sensing (input voltage, DCB voltage, DCB current, phase currents, back-EMF voltage, PFC currents, IGBT module temperature monitoring)
• Supports multiple MCU cards using the PCI Express 64
• EMI filter

Controller cards specifications

Controller cards are an integral part of a high-voltage development platform. A wide portfolio of supported controllers helps ensures that the specific requirements for each application are met. Various controllers are supported, starting with ARM Cortex-M0+ cores, the DSCs, and up to ARM Cortex-M4 cores, with wide connectivity possibilities. Controller cards are connected via the 64-pin PCI Express connector and they are divided into two families, Cortex-based and DSC-based.

Controller cards families - Cortex-based
Key features:
• Accommodates a Target Freescale MCU(KV10, KV3x, KV4x, 56F827xx, 56F84xxx)
• SWD/JTAG isolation up to 5kV
• Cortex-based versions accommodate the integrated Open SDA, supporting
- Mass storage boot loader
- Debugger
- Virtual serial link
• Compatible with CW 10.x, IAR, Keil, KDS
• Design optimized for low noise
• On board isolated power supply, allowing safe debugging
• Daughter card allowing a stand-alone operation
• Test points

Controller cards families - DCS-based
Fast prototyping and fast development are essential requirements for success.
Developing and debugging a high-voltage application with this tool becomes really fast, easy and safe. Moreover, easy porting from one controller to another, with motor control library support, the FreeMASTER and MCAT development tools, significantly contributes towards finalization of the development far earlier than ever before.

This motor control kit is also suitable for those who want to easily learn and develop their motor control application soon, verify existing motor control techniques, or to implement a new one.

The development platform is planned for availability in Q4 2014. More information can be found at
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Processor options for FPGAs

Processors and field-programmable gate arrays (FPGA) often go hand-in-hand in system design. This provides the engineer with flexibility in both software and hardware. In 2002, Xilinx brought the two closer together with the launch of the Virtex II Pro family.

Author: Tony Storey, Application Engineer, Digi-Key

Each Virtex II Pro FPGA contained not one, but two, PowerPC 400-series microprocessors implemented in hardwired logic rather than programmable gates. It was a visionary move that increased the flexibility of the FPGA by providing an efficient way to bring software into the programmable fabric. The PowerPC processor could provide the basis for building complex state machines or hosting real-time operating systems. This permitted an independent subsystem to exist within a larger design.
Today, FPGA densities are so high that a single device can be the heart of a complete embedded system. These devices easily support both the space and performance for a processor, memory and customised logic. Although a hardwired processor sitting alongside the FPGA fabric will take up less die space, many designs now put one or more processor cores into the programmable logic fabric to take advantage of its massive flexibility.
In recent years, FPGA makers have largely settled on the ARM architecture as the one to adopt for hardwired embedded processors. Microsemi was the first to bring support for the ARM architecture to the FPGA successfully. The company’s SmartFusion architecture combined the ARM Cortex-M3 with a non-volatile FPGA fabric based on flash technology.
This allows the hardware-based parts of the system to be active as soon as power is restored, rather than having to wait for the FPGA configuration from external ROM.
The higher-performance Cortex-A9 forms the heart of two major families of FPGAs launched recently by Altera and Xilinx. In both the Altera Cyclone SoC and Xilinx Zynq devices there are two ARM processors, allowing the devices to be used as high-performance compute engines.
As well as bringing the Cortex-M3 to the FPGA market, Microsemi was instrumental in introducing an ARM M-series MCU version for use in standard programmable logic. Optimised for implementation within an FPGA’s programmable fabric, the Cortex-M1 is a streamlined version of the Cortex-M3. The Cortex M1 is designed to not require much more die space than an 8051 core, despite being based on a 32-bit pipeline rather than 8-bit. Like the M3, the M1 runs the Thumb2 instruction set, but with some instructions and features removed. The M1 interrupt structure was simplified to save space; it supports 32 interrupt sources versus the M3’s 256.
The availability of open-source development tools has helped bring other architecture cores into FPGAs. Altera, Lattice and Xilinx each have their own RISC-like processor architectures. Each has been optimised for use within the programmable logic fabric. By bringing their compilation and linking tools into free environments such as Eclipse, the FPGA vendors make it easier for developers to switch from a standard architecture to their own.
Licensing considerations may influence which core and FPGA a designer may wish to use when the design goal is to go to a standard cell ASIC. Some soft MCUs are only licensed for use with a given FPGA supplier’s devices. This limits the ability of the designer to migrate a design to an ASIC. The advantage of these MCU cores is that they have a fully supported design and implementation flow; this makes inserting IP and subsequent development remarkably easy.
The LatticeMico32 has a more flexible licensing arrangement, which has helped to foster the architecture’s use with advocates of open-source hardware. Lattice allows the processor to be used in designs that may be migrated to ASICs supplied through independent foundries or even other FPGA architectures.
Designers need not be limited to vendor-supplied soft-processor cores. Based on the Sparc architecture originally developed by Sun Microsystems, now part of Oracle, the Leon family of cores and the OpenRISC 1200 are open-source IP blocks from independent sources. The cores typically take up more die space than LatticeMico32, Microblaze or Nios – typically 1.5 to 2 times larger in terms of logic elements used in an architecture that uses conventional four-input lookup tables – but provide flexible alternatives to the vendor-supplied cores.
As well as off-the-shelf cores, the programmable nature of the FPGA provides the designer with an excellent opportunity to build custom processors. The Cyclone SoC and Zynq architectures were developed specifically with this use in mind – devices in both families have wide I/O buses to transfer bulk data between the programmable-logic sections and the processor.

Over the years, FPGA suppliers have added support for high-speed computation, particularly for signal-processing applications.
Multipliers can consume a lot of area in a standard architecture based on lookup-table elements. The most efficient way to implement multiplication in programmable cells is to use bit-serial arithmetic. The multipliers are slow because they work by adding and shifting one bit at a time. Bit-serial multipliers excel when used in massively parallel arrays, they can support high aggregate data-rates.
The simplicity and compact nature of the bit-serial multiplier makes it possible to use many of them in a single FPGA. If latency is not important, they still make a good choice.
To speed up processing, FPGA vendors added carry-chain logic to let designers implement faster carry-lookahead and carry-save adders in programmable logic. Many FPGA architectures, including cost-optimised products such as the Altera Cyclone and Xilinx Spartan-6, now include hardware multiplier blocks for use in high-speed DSP applications.
These blocks can be quite narrow to reduce their die consumption but they can easily be tied together to form more sophisticated 32-bit and 64-bit multipliers, using programmable logic cells to add support for more sophisticated features such as floating-point arithmetic. Some architectures provide a variety of DSP cores to suit target applications. These cores contain multiple narrower 9-bit units favoured for image and video processing and wider cores used for audio and communications signals.
Thanks to the programmable nature of the FPGA fabric, it is possible to build coprocessors that adapt to the needs of the system. Partial reconfiguration can allow different coprocessor blocks to be loaded into the fabric, executed and then replaced with another algorithm. For example, in an audio processing algorithm, the FPGA fabric may perform spectral processing using fast Fourier transforms (FFT) followed by filtering using a finite impulse response (FIR) filter loaded into the same section once the spectral analysis has completed.
The programmability of the fabric also helps to streamline data flow through a coprocessor element. In the case of an FFT, implementations of the algorithm in a general-purpose processor are often relatively slow because the ‘butterfly’ data-access pattern the algorithm requires involve repeated fetching and writing of temporary values in cache or main memory – the latency of those accesses may mean the internal arithmetic-logic units are starved of data. The FPGA fabric makes it possible to insert those temporary values into a complex pipeline structure that ensures DSP elements are fed with relevant data at all times.
The FPGA fabric provides advantages for operations that do not fit easily into standard ALUs. For example, cryptographic functions and many algorithms used in digital communications, such as Viterbi and Turbo decoders, often make use of modulo and other non-standard arithmetic.
With full control over the logic elements, an FGPA-based custom ALU will almost always outperform a software emulation running on a standard processor core.
The arrival of languages such as OpenCL is likely to ease the construction of coprocessor elements that can be laid out and torn up as required. Although OpenCL was developed originally to make the compute power of graphics processing units (GPUs) available to programmers more accustomed to working with general-purpose architectures such as ARM or the x86, companies such as Altera have embraced OpenCL as a way of making it easier to build custom compute engines.
OpenCL functions take the form of compute kernels – tight vector-fashioned loops that can be used to process multiple data elements in parallel. OpenCL comprises a runtime environment that loads kernels and respective data into target processors, starting execution and then fetching results once completed. Compilation tools take care of converting the algorithm expressed in the OpenCL language into an implementation suitable for configuration within an FPGA.
Another way to offload software overhead from the processor inside an FPGA is to reduce the frequency of interrupts. Each interrupt demands the processor stop whatever it is doing in order to capture or send a fragment of data through an I/O port, each interrupt involves pushing and register contents onto the stack occupying processor cycles. The analogue compute engine (ACE) in Microsemi’s SmartFusion is a small independent parallel processor that controls the various analogue I/O ports supported by the device.
The ACE combines a sample sequencing engine (SSE) with a post-processing engine (PPE). The SSE captures data from the analogue inputs, passing it to the PPE which can perform functions such as low-pass filtering, to remove noise, and transform the data into a format convenient for the processor. Devolving these functions into hardware ensures they can be used to greatly reduce the interrupt burden on the processor.
Similar techniques can, naturally, be implemented in FPGAs that lack these features to reduce the interrupt load for other processor cores. With an FPGA, there are always many ways to bring software processing and parallelised hardware speed together.

Digi-Key Corporation
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FTDI Chip Adds Further Strength & Depth to its EVE Portfolio with New Software Tools & Arduino Libraries

To provide further assistance to engineers using its Embedded Video Engine (EVE) technology, FTDI Chip can now supply a comprehensive suite of additional
support facilities. These are designed to be utilised with both the established FT800 graphic controller IC and the newly announced FT801, with capacitive touch enabled interface and multi-touch capabilities, which has now been ramped up to full production levels and is available in volume quantities forthwith.

The EVE Emulator Library, is the first of the new support resources. This is a behaviour modelling software tool through which engineers can emulate the display and touch functions of the FT800 (and in the near future for the FT801 in single touch rather than multi-touch mode) without the need for any hardware. It also allows engineers to quickly create demos to show to their project managers or prospective customers. Working on the Windows operating system, it is capable of delivering high level emulation. This tool benefits from an exact SPI/I2C interface configuration and consistent memory map of FT800/FT801 silicon. EVE sample applications employ a hardware abstraction layer (HAL) to make the application logic fully independent from the hardware platform. Sample applications can be adapted on the EVE emulator with the need to alter the application logic.

In addition, FTDI Chip has introduced the release of the VM800BU, which is a development module for the FT800 with a USB interface provided by a FT232H bridging IC. This means when looking to work with EVE-based development modules, it is no longer necessary to source a separate USB converter cable, as the necessary functionality is already present within the board itself.

The EVE Screen Editor is a Windows-based software tool which enables engineers to study display commands and experiment with generating their own display lists by which to control EVE ICs. It can also be utilised to access a number of the various EVE development platforms available (such as the VM800B, VM800C and recently unveiled VM800BU) via FTDI Chip’s MPSSE cable without the need for any supplementary code to be written.

Finally, the expansive set of Arduino libraries offered by FTDI Chip to accompany its EVE offering has been further updated in order to serve both the FT800 and FT801 controller devices. These FT800 Arduino library can be downloaded at:

While the FT801 library can be downloaded at:

“For FTDI Chip ‘Design Made Easy’ is not just a strapline, it represents the company’s core philosophy. It is all about providing our customers with an environment that is conducive to unbounded creativity,” states Paul Huang, Display Product Line Manager at FTDI Chip. “By enhancing and updating the support provisions available for EVE and continuing to expand their scope, we have set the foundations upon which engineers can implement inspirational, highly effective human machine interfaces.”

Now in full production, the FT801 graphic display controller IC is based on FTDI Chip’s award-winning EVE technology. Suitable for WQVGA and QVGA displays this object-oriented device renders image data line-by-line rather than pixel-by-pixel, thereby dispensing with the need for a frame buffer. It has the ability to execute alpha blending and anti-aliasing operations, as well as supporting 18-bit RGB colour with 2-bit dithering for improved colour tone. Midi quality audio functionality is also included. Through the capacitive touch controller interface multiple touch points can be simultaneously determined. This permits detection of complex gestures. US pricing for the FT801 is$4.15 for 1000 units.

For more information on FTDI Chip’s EVE portfolio visit:

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The RZ/A as used in an application example

The key target market for the RZ/A device is the Human Machine Interface market, for driving medium to large TFT panels. The RZ/A family is an ARM cortex A9 based embedded MPU solution that brings many advantages to the HMI application space. The article will be a discussion of the requirements of such an application space as well as of how the RZ/A meets these requirements and offers system level advantages to the design engineering community. The RZ/A features up to 10MB of embedded SRAM on chip, which makes it the largest embedded RAM in the market and the article will show to make best use of this embedded RAM to optimise both system cost and performance of your HMI system.

Author: Robert Kalman, Product Marketing Manager Industrial Communications Business Group, Renesas Electronics Europe GmbH

In June 2013, Renesas released its newest platform. The RZ/A family is aimed firmly at the Human Machine Interface market, for driving medium to large TFT panels. This is a market expanding at an enormous pace. Before Apple took the world by storm, there was the constant dismissive discussion in technical circles about “who would want to have a colour screen on their telephone?” but we were all proved wrong. Apparently, we all do want a colour screen on our phones. It is not just phones either! The number of coffee machines, refrigerators, vending machines and the likes that are fitted with a TFT panel is set to rise significantly over the next few years. I noticed with excitement that in a number of shops recently the piece of plastic upon which a receipt is normally placed such that you can sign it, has now been replaced by a 7-inch TFT display showing advertising for products available in the store. The rise of “bathroom advertising” from companies across Europe and the world shows that soon there will really be no escape from the TFT panel.

So what do you need for your application?

Let’s start by looking at the heart of the problem. What do you actually need in order to drive a TFT screen? Most TFT panels today use a digital RGB interface, whether that be RGB888 or RGB565. The RGB value is a standard whereby the colours red, green and blue of each pixel are represented by the corresponding number of bits. So for 888 each is given a full 8 bits of data (giving 24 bits per pixel), whereas in 565 the red and blue are represented by 5 bits and the green by 6 bits (giving 16 bits per pixel). Alternatively, instead of a standard digital interface a screen could be using an LVDS connector, as is increasingly becoming the standard with larger screens. As such, the RGB signals are transferred over a differential signal, but the format of the data is still the same. So to start with, you need a device that supports the generation of an RGB signal and / or an LVDS interface.
Second to that, the RGB data has to come from a frame buffer, which is typically stored in RAM. This frame buffer is a bitmap image stored in the desired format. Thus, a screen size of WVGA for example (which is 480 × 800) will need for an RGB888 image just over 1MB of RAM to store the image (480 × 800 × 24 bits = 1.125MB).

Memory use for WVGA screen
In addition to this frame buffer containing the current picture being displayed on the screen, a typical application will have a “back buffer” that contains the next picture to be driven to the screen. This way, the CPU can manipulate the next picture without the user seeing a half-manipulated picture flickering on the screen before the CPU is finished.
This system of double buffering is very common and gives an overall higher quality of HMI, but also means that the WVGA screen needs a further 1.125MB of RAM to store the buffer.
The RAM story is sadly not finished, however. In a typical HMI application it is not always necessary to manipulate the whole screen. For example, if an icon or button is pressed, it might animate, glow, rotate or somehow react prior to the action being taken.
In this case, what an HMI designer would do would be to define a different layer of the picture. There would be a background layer that would be unchanged and the icon or button would be a foreground layer, which would then be animated.
However, this obviously also needs additional RAM, not a full screen but “some” more. It depends on the size of the image, but with a 200 × 200 pixel button we would need an additional 100k of RAM. What is also required here is the ability to blend all these different layers with one another, and perhaps apply a level of transparency to some of those pictures. This can be done in software if the CPU is fast enough, or in hardware if it is available.
So, to complete the RAM requirements story, a reasonable HMI application can use in the region of 3MB as frame data for a WVGA screen size. If the code is running on RAM too, as is the case with most processors, then a further 0.5MB of code is needed.
Thus the starting point for a WVGA screen should be to look for a system with a minimum of 3.5MB of RAM.
Of course, the speed of access to the RAM is also very important. As you will have likely just realised, the RAM here is being written to and read from by several different sources concurrently. For example, the front buffer (the original image data) will be read by the IP block to drive the data to the screen. At the same time, the back buffer will be updated by the CPU or by a DMA transfer of a different image. At the same time as this, the CPU may be manipulating the aforementioned icon, and reading its own code from the RAM. This puts a lot of pressure on the bandwidth of the bus to the RAM. This bus is very often the bottleneck in the application, so a good system of bus architecture is required to mitigate the risk of overloading the bus and of the user seeing some half-finished images, or worse still a non-functional GUI.

RZ/A System Block Diagram
Special attention should also be paid to the performance of the CPU. A system delivering 24 frames per second to the screen will need to manipulate and create data (in our example of a WVGA screen) of over 24MB per second. This can be done entirely in software, or in some parts in hardware, but whatever happens the CPU must be fast enough to cover these requirements.
As we are now clearly talking about a processor solution, which is likely not going to have any flash memory on chip, the next requirement is that of a connection to external flash memory. The typical method for today is to use an external parallel NOR flash to store the code and then during boot mode to transfer this code into the RAM to support fast execution. Newer devices, however, support other memory technology to allow system architects to reduce system cost without having the overhead of an “expensive” NOR flash on the PCB.
Most of these applications typically do more than just drive a screen. They need to be connected to the rest of the system too. Automotive applications are typically connected to the CAN or MOST bus. Industrial and consumer devices today generally require Ethernet and USB connections. These connections also mean that the most suitable product will have to not only incorporate the hardware IP, but also have sufficient performance to manage their operation and sufficient code space to support their stacks.

So how about the RZ/A?

The RZ/A family is an ARM Cortex A9 based embedded MPU solution that brings a great many advantages to the HMI application space. The RZ/A features up to 10MB of embedded SRAM on chip, which makes it the largest embedded RAM in the market. There are 3 variations in the family. The RZ/A1H which includes the full 10MB of RAM, the RZ/A1M which has just 5MB of RAM, and the RZ/A1L which includes the lowest 3MB of RAM.
So from the discussion above, where we calculated that the HMI application would need approximately 3.5MB of RAM, the RZ/A1M looks ideally suited to meet these requirements. It is of course possible to find several other solutions on the market that will use external RAM, whether it be DDR or SDRAM, to cover this size of memory but the RZ/A family is the only product that the author is aware of that can offer such a high level of internal RAM.
The RZ/A1H gives the system designer room to increase the screen size and also to decrease the screen size depending on requirements, and create a cost-optimised version for smaller resolution products.
The 400MHz CPU performance is more than enough to run a simple HMI application and maintain communication through whichever protocol the system dictates, because all versions of the RZ/A family include CAN (up to 5 channels) Ethernet, USB (up to 2 channels) and even support MOST in the automotive qualified versions.
In fact, the 400MHz CPU is more than enough due to two unique features of the RZ/A. The first feature is the VDC.
The video display controller from Renesas supports in hardware many of the functions required for creating the final screen image. The VDC will support up to 4 different graphics layers, two of which can be inputs from an external camera. It will also support alpha blending hardware. Alpha blending is a process whereby each pixel is allocated an additional 8-bit alpha value.
This alpha value determines the transparency of the pixel, such that it can be overlaid on top of another pixel to create the resulting image. The VDC also supports chroma-key operation, the most well-known use of which is in “green screen” videography, where a particular colour is defined as transparent so that an object can be overlaid again on another picture. In some systems all of this would be done in software, but the RZ/A does it in hardware, thus the 400MHz in reality equates to a much higher equivalent performance. The VDC also supports the RGB digital connection to a TFT screen as well as the LVDS.
The second performance factor of the RZ/A family that boosts the CPU performance is the removal of the bus bandwidth problem we saw earlier. A quad-core terahertz processor is only as fast as it can get the data. When that data is all stored in a single RAM block to be accessed over a single bus, this is bound to slow down the core. The RZ/A, in contrast, has 5 separate RAM banks. Each bank is connected to its own dedicated 128-bit wide bus, such that it is actually possible to both write to the back buffer, read from the front buffer, manipulate an icon and complete a DMA transfer all whilst running code from the internal RAM. This is a significant performance boost.
Of course, we mentioned earlier that a connection to external flash memory is also needed, and the RZ/A supports all the normal connections to non-volatile memory such as NOR, NAND, SDIO, MMC etc. However, it also has a special SPI Multi-I/O serial flash connection, which supports the new quad SPI protocol. This QSPI can achieve similar or better performance figures to those of parallel flash while providing the economic advantages of serial flash, as well as saving pins on the microprocessor and reducing PCB size.

Simply put: The RZ/A is simple

The newly released RZ/A device from Renesas has been specifically designed for the Human Machine Interface market. There are several requirements in this market which are not unique on their own, but their combination makes the market a difficult one to cover with traditional systems. The need for RAM is large, but not so large that a microprocessor with 128MB of DDR3 RAM is required.
The performance requirements are low, as long as the device is supported by a well-designed display controller, but they are not so low that a microcontroller running at, say, 100MHz could cover them.
The RZ/A contains just enough connectivity for any HMI application, more than enough performance, and a good amount of RAM allowing for flexibility. It is a cost optimised and dedicated solution that will not only profit from the booming market for display technology but also help drive it forward.
Renesas Electronics Europe
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Microsemi Enables OEMs to Expedite Prototyping and

Feature-rich, affordable platform enables OEMs to leverage SmartFusion2’s lowest power consumption in its class, high reliability capabilities and best-in-class security to build highly differentiated products with significant time to market advantage.

Microsemi Corporation, a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, announced the availability of the company’s new leading-edge SmartFusion®2 SoC FPGA Evaluation Kit.
The new SmartFusion2 Evaluation Kit is an easy-to-use, feature-rich, affordable platform designed to enable designers to quickly and easily accelerate evaluation or prototype their application. Utilizing Microsemi’s mainstream SmartFusion2 FPGAs enables original equipment manufacturers (OEMs) to leverage the device’s lowest power consumption in its class, high reliability capabilities and best-in-class security technology to build highly differentiated products that help them gain a significant time to market advantage.
A prime example is that the SmartFusion2 Evaluation Kit allows for simplified development of transceiver I/O-based FPGA designs necessary in today’s PCI Express (PCIe) and Gigabit Ethernet-based systems. For faster evaluation and prototyping, Microsemi’s leading-edge evaluation board is small form-factor PCIe compliant, which can be used on any desktop PC or laptop with a PCIe slot. According to market research firm Infonetics, the carrier Ethernet market will grow to approximately $39 billion in 2017.
The kit offers a comprehensive set of features that include PCIe, Gigabit Ethernet, full-duplex SERDES SMA pairs, DDR memory, SPI Flash, USB On-The-Go and several expansion interfaces that create the needed flexibility for a wide range of application development. With purchase of the evaluation kit, developers also have access to Microsemi’s full array of industry leading development resources such as reference designs and the ability to launch example application demonstrations.

Microsemi Corporation
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EM Microelectronic Releases COiN, a Complete Bluetooth® Smart Beacon

COiN Offers Longest Lasting, Longest Range, Most Secure & Flexible Bluetooth® Beacon

EM Microelectronic introduced the COiN Bluetooth beacon. COiN is a versatile, high performance, low power solution that can be deployed anywhere iBeacon™ technology is used, but which also supports wireless sensor networking and many other applications over Bluetooth® Smart (Bluetooth with a Low Energy Core Configuration) wireless communications.

Low Power

Due to its unique design, COiN consumes less than 20µA average in a typical application, resulting in more than 18 months’ operation from a single CR2032 battery, which is included in the beacon. COiN also contains a built-in pushbutton switch, thus guaranteeing that your beacons have a full charge when they are deployed. Integrated red and green LEDs provide users with feedback about the device’s operating mode. Just click and stick!

Long Range

The COiN’s integrated printed circuit antenna not only minimizes cost, but maximizes communication range. At the 0dBm output power setting, EM Microelectronic’s beacons can be detected 75 meters away by an iPhone® 5S, and at maximum output power, that distance extends up to 120 meters.


Due to COiN’s optimized circuit architecture, it is completely immune to over-the-air attacks, meaning that a well-placed beacon is very secure. It cannot be “hacked” or modified unless the perpetrator has complete physical possession of the device.


COiN is shipped pre-programmed, complete with a Renata CR2032 battery and a weatherproof plastic enclosure for easy deployment, making it suitable for use at outdoor music festivals, sporting events and arenas, and anywhere a beacon is required to withstand the elements.


Though COiN is available in-stock pre-programmed and with a standard housing, the standard COiN hardware and firmware are easily modified to fit most applications. At the most basic level, COiN firmware can easily be modified to change the UUID, MAJOR ID, MINOR ID, output power, and beacon interval. These changes are useful for adapting the beacon for whatever smartphone software application/API is being used, segregating beacon populations and sub-populations, and for optimizing battery lifetime based on the desired use case.
Should more extensive firmware modifications be desired, EM offers a complete development kit. The COiN Development Kit includes five (5) COiN beacons, programming board and programming cable and is fully compatible with EM’s line of software development tools for the EM6819; EM’s ultra-low power microcontroller. Using these tools, customers have complete control over the firmware and can create their own Bluetooth Smart advertising packets and transmit real-time sensor data such as temperature, light level, battery voltage, or other physical phenomena.
The COiN enclosure can be customized to sport any embossed logo desired, making the beacon truly your product. No one will know that you leveraged EM’s decades-long experience and engineering effort and expertise to create your Bluetooth beacon, and we won’t say a word, though enclosure customizations are subject to a minimum purchase volume and tooling charges.
Not much larger than the CR2032 battery that powers it, COiN can be used almost anywhere. To assist in attaching and deploying COiN, EM offers a suite of accessories. The Key Fob Accessory snaps over COiN for attachment to key rings or for hook or loop-based attachment methods such as zip-ties. The Wall Mount Accessory can be nailed or screwed to a solid surface, and then COiN is snapped into place, completely hiding the Wall Mount. COiN can also be snapped into the Watch Band Accessory and any of a number of wrist bands for wrist-worn applications.
“COiN leverages EM’s expertise in ultra-low power wireless and computing as well as our high quality standards and synthesizes them into a high performance, Bluetooth beacon that is ready to deploy out of the box, but flexible enough to be modified for many different applications,” commented Michel Willemin, EM President. “We are already engaged with many companies who are using COiN with their App, API, SDK, or service to improve their performance and lower their overall cost. We believe that the availability of such a flexible, optimized Bluetooth beacon will enable a truly pervasive Internet of Things.”

COiN, the COiN Development Kit and the Key Fob, Wall Mount, and Watch Band accessories are available through your local EM salesperson or distributor.

EM Microelectronic
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Technical Introduction to the RZ/A family

This article is a technical introduction to the RZ/A family, the new embedded processor from Renesas. The device is available in a number of options and a number of configurations designed to give designers a broad choice when designing their TFT drive or GUI application. The article will go into some detail on the features of the RZ/A family, including a technical overview of the memory architecture that includes the world’s largest embedded RAM (up to 10MB) as well as a specially designed bus architecture to ensure fast bus throughput to the memory.

Author: Robert Kalman, Product Marketing Manager Industrial Communications Business Group, Renesas Electronics Europe GmbH

The device also features the 5th generation Video Display Controller from Renesas, which is not only capable of driving a screen up to WXGA size but also of supporting multiple additional functions in hardware which would often be executed in software, so as to allow for full operation at a lower clock speed. The device also features on OpenVG 1.1 compliant block and the article will go on to show how this can be used to improve performance and reduce memory overhead.
The RZ/A family from Renesas is an all new series of embedded MPUs aimed at the Human Machine Interface market. The RZ lineup from Renesas is a new direction taken in the embedded processing arena, based on the Cortex A9 core from ARM running at 400MHz and including all the right IP for creating a high end HMI application without involving the costs, effort and compromises involved in the current HMI application development.

Embedded MPU?

As well one may ask, what does the term “embedded MPU” actually mean? In order to answer this question, we have to have a brief look at the current offering across the MPU / MCU spectrum. Today, an MCU typically contains embedded flash and RAM, running code from the flash but somewhat limited in terms of performance, particularly when it comes to the area we are talking about – the performance level needed for a Human Machine Interface. The alternative today is the classical MPU or microprocessor system which achieves the performance level needed and can significantly exceed it; however, it typically will not have any internal flash and only a small amount of internal RAM. Typical MPUs have their place in the market as do MCUs, of this there is no debate. However, there is certainly a significant gap between the two areas.

MCU system diagram

MPU system diagram

eMPU system diagram

Filling the gap is where the eMPU can be useful. The eMPU, like an MPU, does not contain any embedded Flash and has a CPU core running at a performance that would not be possible with a typical MCU. This performance level can (as with the MPU) only be achieved by running from RAM. In contrast to the microprocessor system, which will use external RAM, the eMPU contains all the RAM that it will need for the application.
As can be seen in the system diagrams below, the MCU is obviously the most simple, but the eMPU offers a compromise offering the performance of an MPU without the complexity associated with it.
The eMPU typically will boot from an external serial flash, compared to an MPU, which will typically use external NOR flash. This can have several advantages:

• It is possible to use the QSPI serial flash block which can achieve even faster performance than the standard NOR flash.
• It requires less PCB space and fewer pins on the eMPU than a 32-bit parallel NOR flash.

The eMPU has enough RAM internally that it does not need to use external RAM, compared to an MPU which will typically use external DDR or SDRAM. This can have several advantages:

• The application is decoupled from the RAM market. Although this is not likely to be seen as a positive point for the average hardware designer, any purchasing team will breathe a sigh of relief to be free of this.
• It requires less PCB space and also fewer pins on the eMPU, and coupled with the use of a serial flash can allow designers to use a much smaller QFP package, allowing for a 2 layer PCB instead of a multi-layer PCB.
• It eliminates the requirement for an additional power supply of 1.8V for the DDR supply.

Now clearly there is a line whereby the performance of an eMPU is not going to reach that of the quad core multi-gigahertz system residing in a desktop PC, but not every HMI system today needs to be built like a PC. There is another way!

The features of the RZ/A devices

The RZ/A features a Cortex A9 core which is clocked at 400MHz and includes the optional IEEE754 compliant double precision floating point unit architecture (VFP) and the optional general purpose 128bit single instruction multiple data (SIMD) NEON extension. These extensions accelerate typical operations in DSP, multimedia and visualisation applications. The core, as is standard on Cortex A9 cores, has 32kB of instruction cache and 32kB of data cache. Additionally it includes 128kB of L2 cache to ensure that even if code is running from external non-volatile memory it can be executed at maximum performance.
The core alone is nothing unusual. The unique feature of this device is the inclusion of 10MB of internal RAM. This RAM is split into 4 separate blocks. Each block is 2MB in size and has a dedicated 128-bit wide bus running at 133MHz. This means that each block can be addressed concurrently by the different peripherals on the chip. At the same time as the CPU can be running code from one block, it can be writing data to a second block, whilst the third block can contain the picture data to be written to the TFT screen and the final block can be used for some DMA access or as the communications buffer for a TCP/IP stack; all of these with no bus collisions.

Diagram of the RAM blocks and the internal bus
This is of course another major benefit of the eMPU architecture. Whilst an MPU has typically a fast bus to the external RAM, there is also only one of them. Thus the likelihood of a bus collision is high.
A feature of the 10MB of SRAM in the RZ/A family is the low-power RAM. In block zero of the RAM there is 128kB of “data-retention” RAM, which is also split down further into smaller blocks. These blocks can remain powered in low power modes and allow for a significantly faster wake up from these modes. The startup code and even the first screen to be driven to the TFT can be saved, thus as soon as the user presses a button or starts the system, it is as near as possible to a live state immediately. This is clearly another major advantage over MPU systems today which in order to achieve the lowest possible power consumption will remove power to the RAM and thus need to boot completely again from scratch.
Another unique feature of the RZ/A family is the SPI Multi-I/O. This peripheral can be thought of as a simple serial SPI block with a few extra enhancements. The first such improvement to the block is that it not only supports standard serial mode but also the new QSPI mode. This mode uses four parallel data lines as opposed to the standard 3 wire serial bus. With the new improved speed of this connection, initial benchmarks are showing a performance improvement in excess of 9 times when compared to the previous SPI modules. It also shows that it is possible to achieve even better performance (approximately 3%) than when accessing parallel external NOR flash, for example. This has the upshot of allowing for a fast boot time without needing to connect a 32-bit bus to a device. The other feature of the SPI Multi-I/O block is the “execute in place” functionality. The block allows the CPU to access the QSPI serial flash as if it were an external linear address space. This feature is also supported by the L2 cache, such that code can be run directly from this external flash. The upshot of this feature is that any critical code that needs to be run fast and regularly can be run from the internal RAM, and then code that does not need to be run regularly can be run from external flash. So although designers are limited to only 10MB of RAM, the amount of code that can be written is limited only to the size of the available external SPI flash.
Finally, from a communications point of view, the device comes with everything that you would expect. There is an Ethernet MAC, two USB 2.0 interfaces supporting both host and device functionality, as well as up to 5 CAN channels.

An overview of the Graphics IP (Video Display Controller and OpenVG)

So now we have learned that the RZ/A family is a fast processor which achieves high performance based on the 10MB of internal memory, and a wide bus avoiding collisions. It also supports a number of peripherals supporting all the standard interfaces one would expect while also allowing system designers to design a system with a low bill of materials cost without compromising performance. All of this is nice, but it doesn’t get to the real crux of the target application yet. How do you drive the screen?
The RZ/A has two features which make driving a screen very simple and allow for an impressive GUI. The first of these features is the VDC5. The VDC5 is the 5th generation of the video display controller from Renesas and is able to drive screens up to a maximum size of 1999 pixels × 2035 lines, making it the most impressive of its kind. The VDC5 actually supports up to 2 channels meaning that two screens can be driven concurrently. The VDC5 also supports standard digital interfaces as well as LVDS, such that the trend in larger screens to use the LVDS interface can also be supported.
The first portion of the VDC is the input controller, which can receive up to two video input signals up to a maximum size of 1440 × 1024. The input controller supports phase compensation as well as horizontal noise correction and contrast correction. The input signals are then passed to the scaler block.
The scaler block (of which there are two per VDC5 channel) can be used to scale the two video inputs either up or down to create the correct size image for the screen. The images can also be rotated and the two video inputs can even be overlaid using alpha blending and a colour look-up table (CLUT). The final images (if both inputs are treated separately) or image (if only one input is used or the two inputs are overlaid) are then stored in a frame buffer in the RAM and passed to the image synthesiser.
The image synthesiser combines up to 4 individual layers to create a single image. When the either only one or no video inputs are being used, these layers are free to be used for other parts of the GUI as separate overlay layer or icons. Through a process of alpha blending and the CLUT, the final single image is created for the screen, and driven to the output controller.
Finally, the output controller takes the generated image and drives it to the TFT screen, either via the LVDS or the digital output, in one of many supported formats: RGB888 (24-bit parallel output), RGB666 (18-bit parallel output), RGB565 (16-bit parallel output) or RGB888 (8-bit serial output).
The operation of the alpha blending and the combination of the multiple layers means that the CPU can be offloaded of this functionality.
The second peripheral of the RZ/A devices that is useful for HMI development is the OpenVG-compliant graphics engine, which is a 2D vector graphics accelerator. The IP accelerates stages 2 to 8 of the OpenVG pipeline by using dedicated hardware and a compliance tested library.
The OpenVG engine can be used to fill the frame buffers and the VDC5 can then be used to drive the image data to the screen.
The advantage of using openVG is that it allows for the use of vector graphics, which can greatly improve the efficiency as well as the “look and feel” of a GUI.
Two simple examples can be used: where an image has to be rotated, the easiest way to do this with a bitmap image is to save the image 360 times, each rotated by 1 degree, and then simply show each picture one after the other.
This is clearly a significant overhead in terms of memory usage and also in terms of bandwidth of the device, while a vector implementation of the same picture can simply be rotated and the support for this rotation is included in hardware in the RZ device. The second example is that of scaling, and in this case a picture paints a thousand words, so I will leave the picture below uncommented.

Putting it all together

The RZ/A, Renesas’ new eMPU, is designed to fill the gap between the traditional MPU and the traditional MCU market spaces. It features up to 10MB of embedded SRAM, and supports a fast wake up from lower power modes. The device only needs a simple and low cost serial flash from which it can boot directly. The 10MB of memory is enough to store both the front and the back buffer for a double buffered HMI application. The RZ’s 10MB of internal RAM is connected to a multi-layered bus and is separated into 2MB blocks, such that the RAM can be both read from and written to by multiple sources concurrently. This enables a high performance Human Machine interface application to run on a system that needs no external RAM and has a low number of pins, available in QFP packages such that designers are able to use a 2 layer PCB.
The RZ/A will never achieve the simplicity of an 8 bit MCU with 16k of ROM, nor will it ever achieve the performance of a quad-core 2GHz Processor, but Renesas believes that your next Human Machine Interface application needs just a little bit more performance than a standard MCU can offer, but without making that big jump to a microprocessor architecture.
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The fundamental components of the Internet of Things

Figure 1: Comparing data rates of RF systems.

The focus of the internet is set to change over the next five years as systems become smarter. According to networking specialist Cisco, 50 billion devices are likely to be connected to the internet by 2020, helping to sustain a $14tr market. The systems that dominate the internet today, such as PCs, laptops, tablets and smartphones, will be dwarfed by the tens of billions of machines with network connections that will relay data to each other with the aim of making life more efficient.
The idea of the internet of things (IoT) dates back to the late 1990s when researchers proposed ideas such as ambient intelligence, in which a forest of smart sensors would monitor environmental conditions, alerting control systems to changes. By enacting changes in response, these control systems can improve efficiency in a wide range of systems, from industrial control through home automation to healthcare. For example, a set of smart sensors dotted around the body, can pick up on health problems that alert the user to a problem through their phone.

Author: Mark Zack, VP Global Semiconductors, Digi-Key

In industrial control, a series of sensors mounted along a production line can detect conditions that may lead to problems such as sudden changes in temperature or excess vibration that may signal a problem in a machine tool or a process going outside its bounds.
There are three fundamental components that combine to form an IoT node: intelligence, sensing, and wireless communications. Wireless connectivity is vital because it will allow sensor nodes to be deployed quickly and easily without the requirement to route network cables to each location.
In order to survive for long periods of time on a single battery charge, an IoT node needs to exhibit low power consumption. Typically, the node will be dormant for long periods of time, waking up for short periods to take a reading and then make a decision on whether to send out an alert based on the change or go back to sleep. A large number of microcontrollers are designed around this core requirement, sporting ultralow-energy sleep modes combined with high-performance instruction pipelines to streamline processing while awake.
A key decision is the type of architecture. A growing number of low-cost microcontrollers from vendors such as Atmel, Freescale, STMicroelectronics and Texas Instruments use 32-bit cores based on architectures such as ARM to deliver high performance at low power and access to a growing range of open-source software that allows applications to be built quickly. However, architectures such as Atmel’s AVR demonstrate that the 8-bit platform still provides a great deal of power, using advanced smart peripherals to collect data from sensor interfaces, and delivering high cost-effectiveness.
There are a number of possible approaches for introducing low-power communications to an IoT node, ranging from purpose-designed protocols such as Zigbee to low-power variants of Bluetooth and Wi-Fi. Some of these protocols offer direct compatibility with the internet protocol (IP). Others rely on a gateway to map between IP packets and the leaner protocols used by the IoT sensor nodes.

Zigbee is a low-power wireless network specification based on the IEEE 802.15.4 (2003) standard that was developed by a group of 16 companies involved in industrial and building automation. A novel aspect of Zigbee compared to many other networking protocols lies in its use of mesh networking. This allows IoT nodes far away from a central controller to use nodes in between to carry their communications. This not only extends the range of a central gateway, it also increases robustness as a transmission can use a number of different routes through the mesh.

Originally launched by Nokia as Wibree in 2006, Bluetooth Low-Energy (BLE) or Bluetooth Smart provides a similar range to classic Bluetooth but with reduced power consumption. In place of the 1MHz channels used by the original Bluetooth protocol, BLE uses a smaller set of wider-bandwidth channels of 2MHz but with a lower peak data rate.
The channel bandwidth is similar to that of Zigbee but with narrower spacing.
A key advantage of BLE is its lower latency, just 3ms versus the 100ms of classic Bluetooth, as well as lower complexity so that its software stack can easily be incorporated into lower-cost microcontrollers. BLE retains support for frequency hopping from the original Bluetooth protocol, which makes it more robust than Zigbee in the presence of strong interfering signals.

Figure 2: Channel arrangements for Zigbee, BluetoothLE and Wi-Fi.
One of the main application areas for BLE is medical instrumentation, where a number of on-body sensors to monitor heart rate, blood pressure, and posture relay their readings at regular intervals to a central controller, which may be a mobile phone or a dedicated medical instrument.
Having been in use in various forms for more than 15 years, Wi-Fi has the benefit of being the most mature wireless-networking radio technology suitable for IoT applications. Through protocols such as WPS, Wi-Fi can offer easy integration into an existing network for devices that have little to no physical user interface.
Of the wireless technologies suitable for IoT applications, Wi-Fi has the best power-per-bit transmission efficiency. Conventional Wi-Fi designs tend to use more energy to maintain a connection while quiescent than protocols such as BLE, which can decrease energy efficiency if the application does not need high bandwidth. However, vendors such as GainSpan have worked on power efficiency in designs such as the GS2000, which combines support for both ZigBee and Wi-Fi on the 2.4Ghz and 5GHz band. These designs put the radio into an energy-saving standby mode if the sensor node does not need to transmit any data. It wakes up only to send data or keep-alive connection packets used to assure central controllers that the node has not failed.
In general, Wi-Fi tends to suit applications where compliance with the IP stack is an advantage, there is a requirement to deliver large amounts of data, such as audio or video, or the remote devices can be powered by external energy sources.

An example of Wi-Fi in use is by Mernok Elektronik of South Africa, which used modules from connectBlue to incorporate wireless networking into the locomotive control and safety management systems of railway systems used in mining.
The modules are used to collect real-time operation data on each vehicle and provide a robust wireless connection across both 2.4GHz and 5GHz frequency bands with support for over-the-air firmware updates and parameter changes.

BLE and Wi-Fi can be used together efficiently as they both support coexistence protocols designed to reduce interference between the two on their common frequency band of 2.4GHz. This coexistence ability lends itself to implementation in gateway designs where BLE is used for connections to sensor nodes and Wi-Fi for relaying aggregated data to a backbone network.
The APx4 from Bluegiga provides an off-the-shelf solution for this, providing support for both Wi-Fi and the full Bluetooth 4.0 software stack that includes BLE, based around a powerful 450MHz ARM9 processor.
A number of integrated microcontrollers and support chipsets from vendors such as Atmel, CSR, Freescale, STMicroelectronics and Texas Instruments provide support for protocols such as BLE, Wi-Fi and ZigBee. For implementations that need flexibility, the configurable radio transceivers made by Lime Microsystems make it easier to deploy nodes that can be programmed with a specific RF interface personality at the point of manufacture to suit different networking needs in the target system.
As the IoT scales up, we can expect more integrated solutions to arrive on the market. But, even at this early stage of development, there are many choices available to the engineer with which to incorporate the three key components of IoT support.

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Silicon Labs Streamlines iOS Accessory Designs with Comprehensive 32-bit Development Kit

Silicon Labs introduced a new 32-bit hardware and firmware development kit designed to accelerate the design of Made for iPod/iPhone/iPad (MFi) accessories and help
product manufacturers get to market quickly.
Leveraging Silicon Labs’ ARM® Cortex®-M3-based SiM3U microcontroller (MCU), the MFI-SIM3U1XX-DK development kit supports the all-digital Lightning connector and protocol stack. The new development kit targets a wide range of accessories for iOS devices including entertainment accessories, device-powered dongles, game controllers and docking stations.
Silicon Labs designed the MFI-SIM3U1XX-DK kit as a turnkey solution to help developers simplify their Lightning-based accessory development projects and speed time to market while meeting the MFi program requirements with ease.
Silicon Labs’ 32-bit development kit provides an exceptionally cost-effective and comprehensive solution for accessory developers. The kit includes everything engineers need to begin developing Lightning-based accessories right away, including a hardware development board, firmware libraries and an example iOS App, which supports Appcessory-style communication between the iOS device and development board. By simplifying the development process, the new 32-bit kit enables MFi licensees to focus on what matters most – the accessory application itself.

The MFI-SIM3U1XX-DK kit enables developers to reduce the cost, complexity and power consumption of accessories designed for iOS devices. The SiM3U MCU features fully-specified analog peripherals, an integrated capacitive touch sense controller, an internal 5V regulator and crystal-less USB support, which eliminates the need for discrete crystal oscillators and reduces bill of materials (BOM) cost, component count and board space. Device-powered accessory applications benefit from the SiM3U MCU’s best-in-class power efficiency. The SiM3U MCU offers ultra-low power consumption with full analog operation down to 1.8 V, achieving a 33 percent lower active current than in-class competitors and a 5-100x lower sleep current, while a low-current USB idle mode ensures the viability of device-powered accessories.

Silicon Labs
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Energy Saving Network Power management (ES-NP)

To meet the European CO2 - emission guidelines, the car manufacturers have investigated all systems with respect to their energy efficiency. Even the smallest load can become a factor in deciding whether a tax of EUR 95 per 1g CO2/km has to be paid or not. Control units not required constantly are now - just like in mobile phones – intended to be put into current saving mode. Two competing network standards are vying for the developer’s attention namely the Pretended Network and the Partial Network. This article analyses each standard in terms of its respective advantages and disadvantages and offers solution approaches.

Figure 1

Challenge - the CO2 tax

Since 2012 everybody is talking about the European CO2 tax for cars. Every car manufacturer selling cars in the EU whose CO2 emission exceeds the regulation limits must pay penalty taxes. The intention behind this is make the industry and the consumers aware of the costs of climate changes and environmental damages caused by the CO2 emissions through a clear price adder.
The CO2 tax is being discussed in public controversially. Heated debates have ensued over the CO2 tax amount, its effectiveness, or the question whether CO2 tax is justified at all.
Actually, the CO2 tax has triggered a long due discussion over a problem, that is, to face the issues of limited resources and climate changes. Besides the emotional debate though, work is long under way to resolve the problems. The car manufacturers have analysed their car models and evaluated potential improvements already before 2012. In each construction segment like combustion engine, air drag, road resistance right up to electrical loads, potential improvements and corresponding costs have been calculated. From this point of view, the CO2 tax motivates innovation for economical processes and efficient use of energy.

Saving CO2 through control units

This article deals with the role of electronic control units which, assisted by the microcontrollers contribute significantly towards reduction of energy consumption in cars. In a typical premium vehicle up to 100 control units - interconnected in a network - are used to help increase the efficiency.
Some of which are active even when a car is parked (e.g. door control and anti-theft protection). In order to assess the increase in efficiency in this segment, the complete chain of factors impacting the efficiency must be reviewed (refer to figure 1).
One of the biggest loads in a control unit is the microcontroller which is powered by a voltage regulator. The voltage regulator in the control unit is powered by the dynamo, which in turn is driven by the combustion engine. This consumes fuel, exhausting thereby CO2. Therefore, the more current a microcontroller requires, the more fuel is consumed and consequently the vehicle exhausts more CO2.
A premium model with 100 control units has up to now been emitting up to 5g CO2/km purely due to the current consumption of the control electronic, NB without a single other electrical load e.g. the headlights or air conditioner ventilator being on. The CO2 tax envisages levying EUR 95 tax per 1g CO2/km per car if weight specific CO2 emission limit is exceeded. Thus, for an emission of 5g CO2/km, a car manufacturer would therefore have to pay up to EUR 475 CO2 tax.
Such assessments have increased awareness even for the smallest energy load. The development departments have been urged to put the control units in the current saving mode as often as possible or even to shut down completely. This idea has been copied from laptops and mobile phones where the displays are switched off and the CPU frequency is reduced if it is idle. Of course, the reduced current consumption is also always coupled with a reduced functionality and additionally the ramp-up time till full functionality is available again is long - just like in case of laptops. Whereas a trailer-light control unit can be switched off completely without any loss of comfort if no trailer is attached to the car; the situation is different though in case of an air conditioner ventilator. Therefore, the engineers must consider and control precisely as to when a control unit is not required in order to save energy at the expense its functionality.

Figure 2

Network of control units

Since in modern cars all control units communicate with each other via a network, the car manufacturers have created standards which define how much and at which point in time control unit current can be saved. One such Software-Standard-Platform is for example the AUTOSAR. Both approaches, namely the “Partial Network” and the “Pretended Network” were defined here.
Common to both approaches is that 2 current saving levels each have been specified. In Pretended Network the “Level 1” and “Level 2”; in Partial Network the “Standby” and “Sleep”. The higher the current reduction, the longer is the “wake-up” time of a control unit till it regains the full functionality (refer to figure 2).
Pretended Network
The Pretended Network follows the so-called Best Practice approach; the currents here - compared to the Partial Network – are even under extremely reduced use of resources very low, presently below 7mA (future target - below 2mA). The lower limit of the current is determined by the presently used standard transceiver which, with its 5mA has the largest share in the total standby current. Especially the volume producers appreciate the advantage that the new Pretended Network control units can operate together with the older units in the same network. This reduces the development risk considerably and also allows continual introduction of this technology within the next generation model. The wake-up time is considerably shorter than in Partial Network because the microcontroller is never fully powered off and the modern current saving modes of microcontroller can be utilized optimally.

Partial Network

Partial Network is the more radical of the two and is also a more expensive approach. A new type of intelligent network transceiver controls the whole control unit. Hereby, standby currents below 0.5 mA are feasible, but it is not a low cost solution. A complete implementation of this standard requires that all control units of a network must be equipped with the intelligent network-transceivers. Another disadvantage besides the additional costs is that the control unit wake-up time out of the maximum current saving mode is relatively long. This is because for the microcontroller it is almost like a cold-start process which can take up to 10 times as long as a warm-start.

Decision: Revolution or Evolution?

Every car manufacturer must ask himself the question: Revolution or evolution - Partial Network or the Pretended Network - or in other words - how much money and efforts one has to spend to achieve the respective CO2 reduction goal.
Thus, the question to be answered is - wouldn't the resources for an expensive network transceiver, additional efforts needed for converting the software of all network control units, and having to live with the slow reaction of the control unit in the maximum current saving mode – be better spent for something different?

Solution approach: Energy Saving Technologies (EST)

In parallel to the relatively recent debate over current saving due to European CO2 tax, Renesas has developed multiple technologies which reduce the current consumption of microcontrollers.
All in all 5 different solution approaches have been realised thereby:

ES-FT: “Energy Saving - Flash Technology”
ES-NP: “Energy Saving - Network Power Management”
ES-LPS: “Energy Saving - Low Power Sampler”
ES-PM: “Energy Saving - Power Modes”
ES-PS: “Energy Saving - Power Scaling”

The first two of these technologies would be reviewed more closely here for implementation in the “Partial Network" or the “Pretended Network".

Energy Saving Flash Technology (ES-FT)

Renesas has achieved a great success in its current 40 nm technology development for automotive microcontrollers with internal Flash.
Renesas developed indigenous transistor technology for its 32-bit microcontrollers, increasing performance while reducing the current consumption by 50% at the same time. This reduces the current consumption in operation mode itself by half, without one having to consider any functional limitation of the control units. This implies an efficiency growth by a factor of 2, a feat which only a few automotive construction segments might be able to duplicate.

Figure 3
Renesas did this by optimising the smallest unit of a microcontroller - the transistor. The total current consumption of a transistor is the sum of its dynamic and the static currents: The static currents are determined by leakage currents which flow as soon as power is applied to the transistor.
The dynamic current flows during switching of transistors, that is, when it changes its logical state (1 or 0).
These currents are determined by the internal capacities of the transistors.
Renesas has succeeded in reducing both by modifying the physical structure of the transistor. The internal transistor capacity was reduced by alteration of the oxide material, and by adapting the transistor geometry, the leakage current could be reduced by a factor of 10. These changes also resulted in higher operating frequencies.

Energy Saving Network Power Management (ES-NP)

In addition, Renesas has optimised the microcontroller digital structure in such a way that maximum current saving modes can be utilised (refer to figure 3), while at the same time the microcontroller can still react to external signals. This is totally taken care of by intelligent IPs (Peripherals) without any CPU interaction. Although in STOP mode the CPU is sleeping, the CAN-IP can participate in the network communication by itself in this configuration. The integrated intelligent message filters wake-up the CPU when a dedicated message type - which is configurable - is detected. Since here the microcontroller is only in STOP mode, it is only a matter of microseconds to execute a warm-start. After wake-up, the CPU can retrieve the message detected by the filter from the CAN-IP and process it.
This configuration is optimal for realising the “Pretended Network Level 2”: Renesas has tested this configuration in a real application and has thereby achieved an average current consumption of 1.58mA. With such a configuration the current consumption of a control unit which previously constantly consumed 105mA, has been reduced to a bare 6.5mA in current saving mode.
This translates into a reduction by 94%. There are no additional costs, no other control unit in network must be renewed and the control units wake-up from their current saving mode in a very short time.
The same configuration, with similar current consumption reduction can also be used to emulate the “Standby Mode” of a Partial Network. Though, in such case, one must live with the disadvantages of a Partial Network described above and that e.g. all network control units which are supposed to support the “Standby Mode” - must be adapted.

Figure 4

Conclusion and Outlook

There are many ways to reduce the current consumption and with that to reduce the CO2 emission. Renesas is of the opinion that an approach combining the latest microcontroller technology with the Pretended Network is the most efficient and the least risky way to reduce the current consumption of control units in cars with reasonable costs (refer to figure 4).
A similar higher demand would also trigger a further development of the last remaining large load; the CAN transceiver with its 5mA accounts for almost 80% of the standby current. With contemporary 0.5mA, control units with standby currents of 2mA in Pretended Network while still retaining all the advantages would then be feasible.
Already today, Renesas automotive series RH850/F1x microcontrollers offer full functionality with 50% less current consumption and the current saving in Pretended- or Partial Network applications is even higher, namely above 90%.
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Enabling a New Generation

The latest addition to Microchip’s PIC32 family increases performance, integration and connectivity.

Author: Bill Hutchings,Senior Product Marketing Manager, MCU32, Microchip Technology

If there is one characteristic that all modern devices strive to demonstrate - irrespective of the end-application - it is responsiveness. The ability to react ‘immediately’ is, of course, an illusion, sustained by the speed with which the microprocessor can respond to an event.
Improving the response time of a microprocessor is often closely influenced by the software it executes, however the underlying metric is the theoretical maximum number of instructions that can be executed per second, or MIPS, subsequently improving this figure has long been the driver for microprocessor evolution.
There are a number of recognised techniques for pushing performance up, as measured using the industry-standard unit of Dhrystone MIPS, or DMIPS. The latest member of the PIC32 family of high performance microcontrollers, the PIC32MZ, harnesses the latest MIPS32 core from Imagination Technologies, which successfully combines many of these techniques to deliver a device that increases performance threefold over its predecessor.
The core at the heart of the PIC32MZ is the recently announced MIPS microAptiv™ core, which features DSP extensions and the microMIPS® instruction set architecture, which allows a combination of 32- and 16-bit instructions to run from memory at near-full rate. In addition, the entire device is capable of running at up to 200MHz, which together results in a device that delivers 330 DMIPS; three times the performance of the PIC32MX family.
The microAptiv DSP extensions provide 159 additional instructions providing single-cycle access to the microarchitecture features that accelerate digital signal processing, such as multiply/accumulate. This means DSP algorithms can execute in as much as 75% fewer instruction cycles than the same algorithm executing on the PIC32MX. The PIC32MZ is the first family to use the microAptiv core, which as mentioned also introduces the microMIPS feature of 16-bit instructions, resulting in significantly higher code density; as much as 30% greater density than the PIC32MX.
The PIC32MZ is also capable of running at higher clock rates, up to 200MHz, which is around twice as fast as the PIC32MX. Together, these features deliver a threefold improvement in raw performance, allowing the PIC32MZ to address applications that demand faster response times when running ever-more complex software.

Built for Embedded Connectivity

The PIC32MZ integrates an Ethernet 10/100 MAC and PHY and it also features the highest ever number of serial channels offered in a PIC device. These features, coupled with a high performance core capable of running multiple protocol stacks simultaneously, makes it the most capable 32-bit MCU for applications targeting embedded connectivity. Another first for a PIC® microcontroller is the addition of an integrated Hi-Speed USB MAC/PHY, complemented by dual CAN ports, which further enforces the PIC32MZ’s connectivity credentials.
An important aspect of any connected device today is security and, here, the PIC32MZ offers a number of features designed to make embedded connectivity more secure. A full-featured hardware crypto engine, with a random number generator, provides high-throughput data encryption/decryption and authentication, such as AES, 3DES, SHA, MD5 and HMAC.
Beyond the high performance core and communications-oriented peripheral set, the PIC32MZ also features two further innovations never before offered in a PIC® microcontroller, both of which are intended to address emerging real-world needs of the target applications; both innovations deal with the need for more sophisticated memory systems.
An increasing number of OEMs are finding that the growing complexity of embedded software means in-field upgrades are becoming unavoidable. Instead of dismissing this trend as a development issue, manufacturers like Microchip are addressing the need head-on, by introducing innovative solutions to in-field software upgrades.
The PIC32MZ is at the leading edge of this effort, by integrating Dual-Panel Flash memory that allows a full software update to take place while the device is in service, executing program code at full speed. It achieves this by dividing the embedded Flash in to two physical and logical blocks, or panels. Each panel has its own charge pump and programming circuit, which means one panel is effectively ghost memory right up to the point when it becomes the main memory. As both panels essentially operate independently, one panel continues to operate at full speed while the other is updated in the background, without interrupting program execution.
Once the software update is installed and validated, the device can be reset and start executing memory from the newly programmed panel.
This feature allows a range of software issue to be addressed in the field without a service interruption, while also retaining the last known good software build in one panel at all times. The benefits of this innovation are far reaching; service calls will be minimised, service interruptions could be avoided entirely and software glitches could be resolved in near ‘real time’.
The other innovation intended to improve memory interfacing is the addition of an SQI port. SQI, or Serial Quad Interface, is a high-speed memory interface protocol that uses up to four wires, as opposed to the more common SPI or I2C interfaces which use only one pin for data exchange. The SQI interface uses a multiplexed bus to access 4-bits - or nibble - of memory at a time when accessing SQI-compatible memory devices, while still retaining SPI-compatibility.
The microAptiv core used in the PIC32MZ features an MMU (Memory Management Unit) and instruction and data caches, and up to 2048 KB of on chip flash and up to 512kbyte of SRAM, capable of supporting multiple protocol stacks running simultaneously, as well as buffer space to support audio processing, and frame buffers to support displays up to WQVGA resolution without the need for an external graphics chip.

Design Support

As the new PIC32MZ family is developed for high-end communications-oriented applications that need improved graphics, faster real-time performance and increased security, it is supported by a range of development kits that give full access to its advanced peripherals and crypto engine (for those family members that feature the optional crypto engine). These are further enhanced by a Multimedia Expansion Board II, Starter Kit Adapter and Plug-In Module which supports the Explore 16 Modular Development Board.
The latest addition to Microchip’s 32-bit MCU family drives performance, connectivity and security to new levels in embedded devices. With a threefold increase in raw processor performance, the addition of 159 DSP-specific instructions and innovative memory subsystem the PIC32MZ is well placed to enable a new generation of embedded devices.
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Microchip expands Arduino™ compatible chipKIT™ eco

Microchip announces the expansion of its Arduino™ compatible chipKIT™ ecosystem, with two new development tools from Digilent, Inc., and an embedded cloud software framework. Digilent’s chipKIT WF32 board minimises the need for users to purchase additional hardware or shields, by
integrating Microchip’s 32-bit PIC32MX695F512L MCU with Full Speed USB 2.0 Host/Device/OTG, its agency-certified MRF24WG0MA Wi-Fi® module and an energy-saving switch-mode power supply that employs Microchip’s MCP16301 DC-DC converter, in addition to a microSD card - all while maintaining an Arduino hardware-compatible form factor. Digilent’s chipKIT Motor Control Shield enables the development of applications using a wide variety of motor types, including servos, steppers and DCs, while allowing users to take advantage of the extra I/O pins found on many of the chipKIT development boards. This additional I/O provides added connectivity and more features than traditional, lower pin-count Arduino shields.
On the software side, an embedded cloud software framework enables designers to easily create “Internet of Things” (IoT) applications with the chipKIT WF32. Additionally, Digilent facilitates the rapid development of wireless HTTP server applications, via its comprehensive sample application that supports static pages loaded from the chipKIT WF32’s microSD card, as well as dynamically generated Web pages.
The combination of Digilent’s chipKIT WF32 base board and its HTTP server example application provides hobbyists, students and academics with an easy way to add wireless connectivity to
their Arduino projects.
This board also provides professional engineers with a rapid method for evaluating Wi-Fi in their embedded designs, and for creating embedded cloud computing services using Exosite. Additionally, as with all chipKIT base boards, the chipKIT WF32 can be connected to Microchip’s PICkit™ 3 programmer/debugger, allowing users to seamlessly move into Microchip’s professional MPLAB® X IDE and XC32 C and C++ compilers.
Robotics applications are particularly popular with hobbyists, students and academics, and their robots are driven by the motor types that the chipKIT Motor Control Shield is designed to support.
Microchip’s PIC32 MCUs enable a high level of integrated features and capabilities onto a single board, reducing development costs and complexity for hobbyists, academics and professional engineers.
Digilent’s chipKIT WF32 (TDGL021) priced at $69.99, and chipKIT Motor Shield (TDGL020) priced at $29.95, are both available today.

Microchip Technology
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Freescale i.MX 6Quad Processor Enables Breakthrough OrCam Eyeglass-Mounted Device for the Visually Impaired

Designing with Freescale seminar in Israel includes product demonstration and keynote by OrCam co-founder, professor Amnon Shashua.

Freescale Semiconductor is powering a compelling new application from Israeli startup, OrCam, that helps people with visual impairments interact more easily with the world around them. The OrCam solution is a compact, eyeglass-mounted device that employs sophisticated computer vision algorithms running on Freescale’s high-performance, energy-efficient i.MX 6Quad applications processor to interpret visual inputs and communicate their meaning in real time to the person wearing the device.
Freescale’s i.MX 6Quad processor provides the OrCam product with the processing power required to execute highly advanced computer vision algorithms. The processor’s integrated camera interface reduces the end-product form factor by eliminating the need for additional components, and the chip’s advanced power management capabilities provide exceptional power efficiency for long battery life.
“The i.MX 6Quad processor delivered outstanding performance well within the power envelope we needed to design a wearable, affordable and intuitive solution for people whose visual impairments prevent them from easily interacting with the world around them,” said Amnon Shashua, co-founder of OrCam and the Sachs professor of computer science at the Hebrew University. “With Freescale’s highly advanced i.MX 6Quad device, OrCam is able to help compensate for lost vision and dramatically improve quality of life for the visually impaired.”

OrCam device powered by i.MX technology from Freescale. (Photo: Business Wire)
The OrCam product is comprised of a small unit mounted on the wearer’s eyeglasses and includes a small camera, microphone and bone conduction headphone. Designed with an intuitive user interface, the wearer simply points at an object or text with his or her finger, and the device then interprets and reads it.
The i.MX 6Quad processor integrates four ARM® Cortex™-A9 cores running up to 1.2 GHz, delivering the processing performance to handle the massive amounts of data captured by the OrCam product’s visual sensor. This performance allows execution of all processing algorithms and software speech codecs on a single chip. i.MX 6Quad processors support computer vision algorithms that allow OrCam to recognize a broad range of inputs, from the faces of friends who walk into a room, to text in newspapers and books, to transit signs, traffic signals and everyday objects of all sorts.
“This design win underscores Freescale’s role as a premier provider of embedded intelligence for the fast-growing wearables and intelligent healthcare markets,” said Shmuel Barkan, joint general manager and director of Sales and Marketing for Freescale Israel. “The i.MX 6Quad applications processor is fueling new categories of applications and, in this instance, is providing the processing power to enable a novel and extremely compelling product that is profoundly transforming the lives of people with visual impairments.”

Freescale Semiconductor
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Why choose when you can have both?

The latest mixed-signal controllers combine the best of both the analogue and digital power-conversion worlds, explains Stephen Stella, of Microchip Technology Inc.

Since the introduction of digital power conversion designers have had a clear choice between using analogue or digital for their designs. Each approach has its own distinct benefits as well as drawbacks, but the development of mixed-signal or hybrid controllers is making it possible for designers to combine the best of both power-conversion worlds.

Analogue for performance

The advantage of analogue power conversion is that it offers very efficient control, whilst the down-side is that it gives designers very little flexibility. Once the performance tradeoffs have been evaluated for each design, the chosen optimisation path is applied across the whole load profile and across the full power-conversion operating range.
Using this single level of optimisation across a design’s full power-conversion spectrum has been the industry standard for many years because, whilst it is inherently inflexible, it does deliver efficient control. However, recent government regulations, and the increasing expectations of end-users, are driving designers to achieve greater efficiency. This is pushing analogue power conversion to the limit of its efficiency and persuading many designers to make the change to digital power conversion.

Digital for flexibility

The main benefit of digital power conversion is that it offers the flexibility that analogue conversion lacks. It replaces one level of power-conversion optimisation with multi-point optimisation. It also provides the ability to communicate with the system, enabling power conversion to become part of the overall optimisation of the system’s long-term performance.
The disadvantage of digital power conversion is that this flexibility comes at the price. The digital approach increases system complexity because the analogue feedback from the system needs to be digitised before it can be used for power management. This means adding an analogue-to-digital converter, and also a high-speed microcontroller or digital signal processor to provide the processing power to achieve digital control.
The speed of the A/D conversion and the computational speed of the MCU/DSP determines the bandwidth of the digital control loop. So, if a design needs more bandwidth, it needs faster and more costly ADCs and MCUs.
Another factor is that digital-control techniques are very different to the techniques needed for analogue control. Making the switch from analogue to digital requires significant investment in the skills, resources, tools and processes required for digital design and software engineering. This investment can be a significant barrier to some companies.

The combined strength of hybrid controllers

Component manufacturers have addressed this dilemma by eliminating the choice between analogue and digital design with mixed-signal, or hybrid, controllers. Combining the strengths of both analogue and digital power conversion, hybrid controllers offset the weaknesses which are inherent in each approach. This enables designers to achieve the

Figure 1: Block diagram of the MCP19111 hybrid controller.
flexibility of a digital solution with the efficiency, load regulation and transient response of analogue power conversion. It also eliminates the need for designers to learn specialised skills or invest in new design resources and processes. Figure 1 shows the block diagram of Microchip’s MCP19111. This hybrid controller integrates a peak current-mode analogue controller with a small, 8-bit microcontroller. By performing power regulation in the analogue domain, the MCP19111’s integrated 8-bit microcontroller provides enough processing power to monitor and adjust the performance of the analogue controller.
Also on-board the MCP19111 are on-chip power MOSFET drivers and a mid-voltage LDO. This high level of integration enables the MCP19111 to significantly reduce the number of external components that are needed for power conversion whilst introducing a degree of flexibility that is not possible with analogue-only power conversion. A very wide operating voltage range of 4.5 to 32V operating range provides even more flexibility for the designer.
The introduction of hybrid or mixed-signal power conversion controllers offers designers the combination of the performance of analogue conversion, with the flexibility of digital control, at a cost that makes it accessible to a very wide range of applications. Whilst some designers will continue to make the choice and accept the limitations of analogue-only or digital-only power conversion, others will combine the best of both worlds by choosing the performance and flexibility of hybrid controllers.
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