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The RZ/A as used in an application example

The key target market for the RZ/A device is the Human Machine Interface market, for driving medium to large TFT panels. The RZ/A family is an ARM cortex A9 based embedded MPU solution that brings many advantages to the HMI application space. The article will be a discussion of the requirements of such an application space as well as of how the RZ/A meets these requirements and offers system level advantages to the design engineering community. The RZ/A features up to 10MB of embedded SRAM on chip, which makes it the largest embedded RAM in the market and the article will show to make best use of this embedded RAM to optimise both system cost and performance of your HMI system.



Author: Robert Kalman, Product Marketing Manager Industrial Communications Business Group, Renesas Electronics Europe GmbH

In June 2013, Renesas released its newest platform. The RZ/A family is aimed firmly at the Human Machine Interface market, for driving medium to large TFT panels. This is a market expanding at an enormous pace. Before Apple took the world by storm, there was the constant dismissive discussion in technical circles about “who would want to have a colour screen on their telephone?” but we were all proved wrong. Apparently, we all do want a colour screen on our phones. It is not just phones either! The number of coffee machines, refrigerators, vending machines and the likes that are fitted with a TFT panel is set to rise significantly over the next few years. I noticed with excitement that in a number of shops recently the piece of plastic upon which a receipt is normally placed such that you can sign it, has now been replaced by a 7-inch TFT display showing advertising for products available in the store. The rise of “bathroom advertising” from companies across Europe and the world shows that soon there will really be no escape from the TFT panel.

So what do you need for your application?


Let’s start by looking at the heart of the problem. What do you actually need in order to drive a TFT screen? Most TFT panels today use a digital RGB interface, whether that be RGB888 or RGB565. The RGB value is a standard whereby the colours red, green and blue of each pixel are represented by the corresponding number of bits. So for 888 each is given a full 8 bits of data (giving 24 bits per pixel), whereas in 565 the red and blue are represented by 5 bits and the green by 6 bits (giving 16 bits per pixel). Alternatively, instead of a standard digital interface a screen could be using an LVDS connector, as is increasingly becoming the standard with larger screens. As such, the RGB signals are transferred over a differential signal, but the format of the data is still the same. So to start with, you need a device that supports the generation of an RGB signal and / or an LVDS interface.
Second to that, the RGB data has to come from a frame buffer, which is typically stored in RAM. This frame buffer is a bitmap image stored in the desired format. Thus, a screen size of WVGA for example (which is 480 × 800) will need for an RGB888 image just over 1MB of RAM to store the image (480 × 800 × 24 bits = 1.125MB).


Memory use for WVGA screen
In addition to this frame buffer containing the current picture being displayed on the screen, a typical application will have a “back buffer” that contains the next picture to be driven to the screen. This way, the CPU can manipulate the next picture without the user seeing a half-manipulated picture flickering on the screen before the CPU is finished.
This system of double buffering is very common and gives an overall higher quality of HMI, but also means that the WVGA screen needs a further 1.125MB of RAM to store the buffer.
The RAM story is sadly not finished, however. In a typical HMI application it is not always necessary to manipulate the whole screen. For example, if an icon or button is pressed, it might animate, glow, rotate or somehow react prior to the action being taken.
In this case, what an HMI designer would do would be to define a different layer of the picture. There would be a background layer that would be unchanged and the icon or button would be a foreground layer, which would then be animated.
However, this obviously also needs additional RAM, not a full screen but “some” more. It depends on the size of the image, but with a 200 × 200 pixel button we would need an additional 100k of RAM. What is also required here is the ability to blend all these different layers with one another, and perhaps apply a level of transparency to some of those pictures. This can be done in software if the CPU is fast enough, or in hardware if it is available.
So, to complete the RAM requirements story, a reasonable HMI application can use in the region of 3MB as frame data for a WVGA screen size. If the code is running on RAM too, as is the case with most processors, then a further 0.5MB of code is needed.
Thus the starting point for a WVGA screen should be to look for a system with a minimum of 3.5MB of RAM.
Of course, the speed of access to the RAM is also very important. As you will have likely just realised, the RAM here is being written to and read from by several different sources concurrently. For example, the front buffer (the original image data) will be read by the IP block to drive the data to the screen. At the same time, the back buffer will be updated by the CPU or by a DMA transfer of a different image. At the same time as this, the CPU may be manipulating the aforementioned icon, and reading its own code from the RAM. This puts a lot of pressure on the bandwidth of the bus to the RAM. This bus is very often the bottleneck in the application, so a good system of bus architecture is required to mitigate the risk of overloading the bus and of the user seeing some half-finished images, or worse still a non-functional GUI.

RZ/A System Block Diagram
Special attention should also be paid to the performance of the CPU. A system delivering 24 frames per second to the screen will need to manipulate and create data (in our example of a WVGA screen) of over 24MB per second. This can be done entirely in software, or in some parts in hardware, but whatever happens the CPU must be fast enough to cover these requirements.
As we are now clearly talking about a processor solution, which is likely not going to have any flash memory on chip, the next requirement is that of a connection to external flash memory. The typical method for today is to use an external parallel NOR flash to store the code and then during boot mode to transfer this code into the RAM to support fast execution. Newer devices, however, support other memory technology to allow system architects to reduce system cost without having the overhead of an “expensive” NOR flash on the PCB.
Most of these applications typically do more than just drive a screen. They need to be connected to the rest of the system too. Automotive applications are typically connected to the CAN or MOST bus. Industrial and consumer devices today generally require Ethernet and USB connections. These connections also mean that the most suitable product will have to not only incorporate the hardware IP, but also have sufficient performance to manage their operation and sufficient code space to support their stacks.

So how about the RZ/A?


The RZ/A family is an ARM Cortex A9 based embedded MPU solution that brings a great many advantages to the HMI application space. The RZ/A features up to 10MB of embedded SRAM on chip, which makes it the largest embedded RAM in the market. There are 3 variations in the family. The RZ/A1H which includes the full 10MB of RAM, the RZ/A1M which has just 5MB of RAM, and the RZ/A1L which includes the lowest 3MB of RAM.
So from the discussion above, where we calculated that the HMI application would need approximately 3.5MB of RAM, the RZ/A1M looks ideally suited to meet these requirements. It is of course possible to find several other solutions on the market that will use external RAM, whether it be DDR or SDRAM, to cover this size of memory but the RZ/A family is the only product that the author is aware of that can offer such a high level of internal RAM.
The RZ/A1H gives the system designer room to increase the screen size and also to decrease the screen size depending on requirements, and create a cost-optimised version for smaller resolution products.
The 400MHz CPU performance is more than enough to run a simple HMI application and maintain communication through whichever protocol the system dictates, because all versions of the RZ/A family include CAN (up to 5 channels) Ethernet, USB (up to 2 channels) and even support MOST in the automotive qualified versions.
In fact, the 400MHz CPU is more than enough due to two unique features of the RZ/A. The first feature is the VDC.
The video display controller from Renesas supports in hardware many of the functions required for creating the final screen image. The VDC will support up to 4 different graphics layers, two of which can be inputs from an external camera. It will also support alpha blending hardware. Alpha blending is a process whereby each pixel is allocated an additional 8-bit alpha value.
This alpha value determines the transparency of the pixel, such that it can be overlaid on top of another pixel to create the resulting image. The VDC also supports chroma-key operation, the most well-known use of which is in “green screen” videography, where a particular colour is defined as transparent so that an object can be overlaid again on another picture. In some systems all of this would be done in software, but the RZ/A does it in hardware, thus the 400MHz in reality equates to a much higher equivalent performance. The VDC also supports the RGB digital connection to a TFT screen as well as the LVDS.
The second performance factor of the RZ/A family that boosts the CPU performance is the removal of the bus bandwidth problem we saw earlier. A quad-core terahertz processor is only as fast as it can get the data. When that data is all stored in a single RAM block to be accessed over a single bus, this is bound to slow down the core. The RZ/A, in contrast, has 5 separate RAM banks. Each bank is connected to its own dedicated 128-bit wide bus, such that it is actually possible to both write to the back buffer, read from the front buffer, manipulate an icon and complete a DMA transfer all whilst running code from the internal RAM. This is a significant performance boost.
Of course, we mentioned earlier that a connection to external flash memory is also needed, and the RZ/A supports all the normal connections to non-volatile memory such as NOR, NAND, SDIO, MMC etc. However, it also has a special SPI Multi-I/O serial flash connection, which supports the new quad SPI protocol. This QSPI can achieve similar or better performance figures to those of parallel flash while providing the economic advantages of serial flash, as well as saving pins on the microprocessor and reducing PCB size.

Simply put: The RZ/A is simple


The newly released RZ/A device from Renesas has been specifically designed for the Human Machine Interface market. There are several requirements in this market which are not unique on their own, but their combination makes the market a difficult one to cover with traditional systems. The need for RAM is large, but not so large that a microprocessor with 128MB of DDR3 RAM is required.
The performance requirements are low, as long as the device is supported by a well-designed display controller, but they are not so low that a microcontroller running at, say, 100MHz could cover them.
The RZ/A contains just enough connectivity for any HMI application, more than enough performance, and a good amount of RAM allowing for flexibility. It is a cost optimised and dedicated solution that will not only profit from the booming market for display technology but also help drive it forward.
Renesas Electronics Europe
www.renesas.com
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Microsemi Enables OEMs to Expedite Prototyping and

Feature-rich, affordable platform enables OEMs to leverage SmartFusion2’s lowest power consumption in its class, high reliability capabilities and best-in-class security to build highly differentiated products with significant time to market advantage.


Microsemi Corporation, a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, announced the availability of the company’s new leading-edge SmartFusion®2 SoC FPGA Evaluation Kit.
The new SmartFusion2 Evaluation Kit is an easy-to-use, feature-rich, affordable platform designed to enable designers to quickly and easily accelerate evaluation or prototype their application. Utilizing Microsemi’s mainstream SmartFusion2 FPGAs enables original equipment manufacturers (OEMs) to leverage the device’s lowest power consumption in its class, high reliability capabilities and best-in-class security technology to build highly differentiated products that help them gain a significant time to market advantage.
A prime example is that the SmartFusion2 Evaluation Kit allows for simplified development of transceiver I/O-based FPGA designs necessary in today’s PCI Express (PCIe) and Gigabit Ethernet-based systems. For faster evaluation and prototyping, Microsemi’s leading-edge evaluation board is small form-factor PCIe compliant, which can be used on any desktop PC or laptop with a PCIe slot. According to market research firm Infonetics, the carrier Ethernet market will grow to approximately $39 billion in 2017.
The kit offers a comprehensive set of features that include PCIe, Gigabit Ethernet, full-duplex SERDES SMA pairs, DDR memory, SPI Flash, USB On-The-Go and several expansion interfaces that create the needed flexibility for a wide range of application development. With purchase of the evaluation kit, developers also have access to Microsemi’s full array of industry leading development resources such as reference designs and the ability to launch example application demonstrations.

Microsemi Corporation
www.microsemi.com
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EM Microelectronic Releases COiN, a Complete Bluetooth® Smart Beacon

COiN Offers Longest Lasting, Longest Range, Most Secure & Flexible Bluetooth® Beacon


EM Microelectronic introduced the COiN Bluetooth beacon. COiN is a versatile, high performance, low power solution that can be deployed anywhere iBeacon™ technology is used, but which also supports wireless sensor networking and many other applications over Bluetooth® Smart (Bluetooth with a Low Energy Core Configuration) wireless communications.

Low Power


Due to its unique design, COiN consumes less than 20µA average in a typical application, resulting in more than 18 months’ operation from a single CR2032 battery, which is included in the beacon. COiN also contains a built-in pushbutton switch, thus guaranteeing that your beacons have a full charge when they are deployed. Integrated red and green LEDs provide users with feedback about the device’s operating mode. Just click and stick!

Long Range


The COiN’s integrated printed circuit antenna not only minimizes cost, but maximizes communication range. At the 0dBm output power setting, EM Microelectronic’s beacons can be detected 75 meters away by an iPhone® 5S, and at maximum output power, that distance extends up to 120 meters.

Secure


Due to COiN’s optimized circuit architecture, it is completely immune to over-the-air attacks, meaning that a well-placed beacon is very secure. It cannot be “hacked” or modified unless the perpetrator has complete physical possession of the device.

Weatherproof


COiN is shipped pre-programmed, complete with a Renata CR2032 battery and a weatherproof plastic enclosure for easy deployment, making it suitable for use at outdoor music festivals, sporting events and arenas, and anywhere a beacon is required to withstand the elements.

Flexible


Though COiN is available in-stock pre-programmed and with a standard housing, the standard COiN hardware and firmware are easily modified to fit most applications. At the most basic level, COiN firmware can easily be modified to change the UUID, MAJOR ID, MINOR ID, output power, and beacon interval. These changes are useful for adapting the beacon for whatever smartphone software application/API is being used, segregating beacon populations and sub-populations, and for optimizing battery lifetime based on the desired use case.
Should more extensive firmware modifications be desired, EM offers a complete development kit. The COiN Development Kit includes five (5) COiN beacons, programming board and programming cable and is fully compatible with EM’s line of software development tools for the EM6819; EM’s ultra-low power microcontroller. Using these tools, customers have complete control over the firmware and can create their own Bluetooth Smart advertising packets and transmit real-time sensor data such as temperature, light level, battery voltage, or other physical phenomena.
The COiN enclosure can be customized to sport any embossed logo desired, making the beacon truly your product. No one will know that you leveraged EM’s decades-long experience and engineering effort and expertise to create your Bluetooth beacon, and we won’t say a word, though enclosure customizations are subject to a minimum purchase volume and tooling charges.
Not much larger than the CR2032 battery that powers it, COiN can be used almost anywhere. To assist in attaching and deploying COiN, EM offers a suite of accessories. The Key Fob Accessory snaps over COiN for attachment to key rings or for hook or loop-based attachment methods such as zip-ties. The Wall Mount Accessory can be nailed or screwed to a solid surface, and then COiN is snapped into place, completely hiding the Wall Mount. COiN can also be snapped into the Watch Band Accessory and any of a number of wrist bands for wrist-worn applications.
“COiN leverages EM’s expertise in ultra-low power wireless and computing as well as our high quality standards and synthesizes them into a high performance, Bluetooth beacon that is ready to deploy out of the box, but flexible enough to be modified for many different applications,” commented Michel Willemin, EM President. “We are already engaged with many companies who are using COiN with their App, API, SDK, or service to improve their performance and lower their overall cost. We believe that the availability of such a flexible, optimized Bluetooth beacon will enable a truly pervasive Internet of Things.”

Availability
COiN, the COiN Development Kit and the Key Fob, Wall Mount, and Watch Band accessories are available through your local EM salesperson or distributor.

EM Microelectronic
www.emmicroelectronic.com
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Technical Introduction to the RZ/A family

This article is a technical introduction to the RZ/A family, the new embedded processor from Renesas. The device is available in a number of options and a number of configurations designed to give designers a broad choice when designing their TFT drive or GUI application. The article will go into some detail on the features of the RZ/A family, including a technical overview of the memory architecture that includes the world’s largest embedded RAM (up to 10MB) as well as a specially designed bus architecture to ensure fast bus throughput to the memory.



Author: Robert Kalman, Product Marketing Manager Industrial Communications Business Group, Renesas Electronics Europe GmbH

The device also features the 5th generation Video Display Controller from Renesas, which is not only capable of driving a screen up to WXGA size but also of supporting multiple additional functions in hardware which would often be executed in software, so as to allow for full operation at a lower clock speed. The device also features on OpenVG 1.1 compliant block and the article will go on to show how this can be used to improve performance and reduce memory overhead.
The RZ/A family from Renesas is an all new series of embedded MPUs aimed at the Human Machine Interface market. The RZ lineup from Renesas is a new direction taken in the embedded processing arena, based on the Cortex A9 core from ARM running at 400MHz and including all the right IP for creating a high end HMI application without involving the costs, effort and compromises involved in the current HMI application development.

Embedded MPU?


As well one may ask, what does the term “embedded MPU” actually mean? In order to answer this question, we have to have a brief look at the current offering across the MPU / MCU spectrum. Today, an MCU typically contains embedded flash and RAM, running code from the flash but somewhat limited in terms of performance, particularly when it comes to the area we are talking about – the performance level needed for a Human Machine Interface. The alternative today is the classical MPU or microprocessor system which achieves the performance level needed and can significantly exceed it; however, it typically will not have any internal flash and only a small amount of internal RAM. Typical MPUs have their place in the market as do MCUs, of this there is no debate. However, there is certainly a significant gap between the two areas.

MCU system diagram


MPU system diagram


eMPU system diagram

Filling the gap is where the eMPU can be useful. The eMPU, like an MPU, does not contain any embedded Flash and has a CPU core running at a performance that would not be possible with a typical MCU. This performance level can (as with the MPU) only be achieved by running from RAM. In contrast to the microprocessor system, which will use external RAM, the eMPU contains all the RAM that it will need for the application.
As can be seen in the system diagrams below, the MCU is obviously the most simple, but the eMPU offers a compromise offering the performance of an MPU without the complexity associated with it.
The eMPU typically will boot from an external serial flash, compared to an MPU, which will typically use external NOR flash. This can have several advantages:

• It is possible to use the QSPI serial flash block which can achieve even faster performance than the standard NOR flash.
• It requires less PCB space and fewer pins on the eMPU than a 32-bit parallel NOR flash.

The eMPU has enough RAM internally that it does not need to use external RAM, compared to an MPU which will typically use external DDR or SDRAM. This can have several advantages:

• The application is decoupled from the RAM market. Although this is not likely to be seen as a positive point for the average hardware designer, any purchasing team will breathe a sigh of relief to be free of this.
• It requires less PCB space and also fewer pins on the eMPU, and coupled with the use of a serial flash can allow designers to use a much smaller QFP package, allowing for a 2 layer PCB instead of a multi-layer PCB.
• It eliminates the requirement for an additional power supply of 1.8V for the DDR supply.

Now clearly there is a line whereby the performance of an eMPU is not going to reach that of the quad core multi-gigahertz system residing in a desktop PC, but not every HMI system today needs to be built like a PC. There is another way!

The features of the RZ/A devices


The RZ/A features a Cortex A9 core which is clocked at 400MHz and includes the optional IEEE754 compliant double precision floating point unit architecture (VFP) and the optional general purpose 128bit single instruction multiple data (SIMD) NEON extension. These extensions accelerate typical operations in DSP, multimedia and visualisation applications. The core, as is standard on Cortex A9 cores, has 32kB of instruction cache and 32kB of data cache. Additionally it includes 128kB of L2 cache to ensure that even if code is running from external non-volatile memory it can be executed at maximum performance.
The core alone is nothing unusual. The unique feature of this device is the inclusion of 10MB of internal RAM. This RAM is split into 4 separate blocks. Each block is 2MB in size and has a dedicated 128-bit wide bus running at 133MHz. This means that each block can be addressed concurrently by the different peripherals on the chip. At the same time as the CPU can be running code from one block, it can be writing data to a second block, whilst the third block can contain the picture data to be written to the TFT screen and the final block can be used for some DMA access or as the communications buffer for a TCP/IP stack; all of these with no bus collisions.

Diagram of the RAM blocks and the internal bus
This is of course another major benefit of the eMPU architecture. Whilst an MPU has typically a fast bus to the external RAM, there is also only one of them. Thus the likelihood of a bus collision is high.
A feature of the 10MB of SRAM in the RZ/A family is the low-power RAM. In block zero of the RAM there is 128kB of “data-retention” RAM, which is also split down further into smaller blocks. These blocks can remain powered in low power modes and allow for a significantly faster wake up from these modes. The startup code and even the first screen to be driven to the TFT can be saved, thus as soon as the user presses a button or starts the system, it is as near as possible to a live state immediately. This is clearly another major advantage over MPU systems today which in order to achieve the lowest possible power consumption will remove power to the RAM and thus need to boot completely again from scratch.
Another unique feature of the RZ/A family is the SPI Multi-I/O. This peripheral can be thought of as a simple serial SPI block with a few extra enhancements. The first such improvement to the block is that it not only supports standard serial mode but also the new QSPI mode. This mode uses four parallel data lines as opposed to the standard 3 wire serial bus. With the new improved speed of this connection, initial benchmarks are showing a performance improvement in excess of 9 times when compared to the previous SPI modules. It also shows that it is possible to achieve even better performance (approximately 3%) than when accessing parallel external NOR flash, for example. This has the upshot of allowing for a fast boot time without needing to connect a 32-bit bus to a device. The other feature of the SPI Multi-I/O block is the “execute in place” functionality. The block allows the CPU to access the QSPI serial flash as if it were an external linear address space. This feature is also supported by the L2 cache, such that code can be run directly from this external flash. The upshot of this feature is that any critical code that needs to be run fast and regularly can be run from the internal RAM, and then code that does not need to be run regularly can be run from external flash. So although designers are limited to only 10MB of RAM, the amount of code that can be written is limited only to the size of the available external SPI flash.
Finally, from a communications point of view, the device comes with everything that you would expect. There is an Ethernet MAC, two USB 2.0 interfaces supporting both host and device functionality, as well as up to 5 CAN channels.

An overview of the Graphics IP (Video Display Controller and OpenVG)


So now we have learned that the RZ/A family is a fast processor which achieves high performance based on the 10MB of internal memory, and a wide bus avoiding collisions. It also supports a number of peripherals supporting all the standard interfaces one would expect while also allowing system designers to design a system with a low bill of materials cost without compromising performance. All of this is nice, but it doesn’t get to the real crux of the target application yet. How do you drive the screen?
The RZ/A has two features which make driving a screen very simple and allow for an impressive GUI. The first of these features is the VDC5. The VDC5 is the 5th generation of the video display controller from Renesas and is able to drive screens up to a maximum size of 1999 pixels × 2035 lines, making it the most impressive of its kind. The VDC5 actually supports up to 2 channels meaning that two screens can be driven concurrently. The VDC5 also supports standard digital interfaces as well as LVDS, such that the trend in larger screens to use the LVDS interface can also be supported.
The first portion of the VDC is the input controller, which can receive up to two video input signals up to a maximum size of 1440 × 1024. The input controller supports phase compensation as well as horizontal noise correction and contrast correction. The input signals are then passed to the scaler block.
The scaler block (of which there are two per VDC5 channel) can be used to scale the two video inputs either up or down to create the correct size image for the screen. The images can also be rotated and the two video inputs can even be overlaid using alpha blending and a colour look-up table (CLUT). The final images (if both inputs are treated separately) or image (if only one input is used or the two inputs are overlaid) are then stored in a frame buffer in the RAM and passed to the image synthesiser.
The image synthesiser combines up to 4 individual layers to create a single image. When the either only one or no video inputs are being used, these layers are free to be used for other parts of the GUI as separate overlay layer or icons. Through a process of alpha blending and the CLUT, the final single image is created for the screen, and driven to the output controller.
Finally, the output controller takes the generated image and drives it to the TFT screen, either via the LVDS or the digital output, in one of many supported formats: RGB888 (24-bit parallel output), RGB666 (18-bit parallel output), RGB565 (16-bit parallel output) or RGB888 (8-bit serial output).
The operation of the alpha blending and the combination of the multiple layers means that the CPU can be offloaded of this functionality.
The second peripheral of the RZ/A devices that is useful for HMI development is the OpenVG-compliant graphics engine, which is a 2D vector graphics accelerator. The IP accelerates stages 2 to 8 of the OpenVG pipeline by using dedicated hardware and a compliance tested library.
The OpenVG engine can be used to fill the frame buffers and the VDC5 can then be used to drive the image data to the screen.
The advantage of using openVG is that it allows for the use of vector graphics, which can greatly improve the efficiency as well as the “look and feel” of a GUI.
Two simple examples can be used: where an image has to be rotated, the easiest way to do this with a bitmap image is to save the image 360 times, each rotated by 1 degree, and then simply show each picture one after the other.
This is clearly a significant overhead in terms of memory usage and also in terms of bandwidth of the device, while a vector implementation of the same picture can simply be rotated and the support for this rotation is included in hardware in the RZ device. The second example is that of scaling, and in this case a picture paints a thousand words, so I will leave the picture below uncommented.

Putting it all together


The RZ/A, Renesas’ new eMPU, is designed to fill the gap between the traditional MPU and the traditional MCU market spaces. It features up to 10MB of embedded SRAM, and supports a fast wake up from lower power modes. The device only needs a simple and low cost serial flash from which it can boot directly. The 10MB of memory is enough to store both the front and the back buffer for a double buffered HMI application. The RZ’s 10MB of internal RAM is connected to a multi-layered bus and is separated into 2MB blocks, such that the RAM can be both read from and written to by multiple sources concurrently. This enables a high performance Human Machine interface application to run on a system that needs no external RAM and has a low number of pins, available in QFP packages such that designers are able to use a 2 layer PCB.
The RZ/A will never achieve the simplicity of an 8 bit MCU with 16k of ROM, nor will it ever achieve the performance of a quad-core 2GHz Processor, but Renesas believes that your next Human Machine Interface application needs just a little bit more performance than a standard MCU can offer, but without making that big jump to a microprocessor architecture.

www.renesas.com
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The fundamental components of the Internet of Things


Figure 1: Comparing data rates of RF systems.

The focus of the internet is set to change over the next five years as systems become smarter. According to networking specialist Cisco, 50 billion devices are likely to be connected to the internet by 2020, helping to sustain a $14tr market. The systems that dominate the internet today, such as PCs, laptops, tablets and smartphones, will be dwarfed by the tens of billions of machines with network connections that will relay data to each other with the aim of making life more efficient.
The idea of the internet of things (IoT) dates back to the late 1990s when researchers proposed ideas such as ambient intelligence, in which a forest of smart sensors would monitor environmental conditions, alerting control systems to changes. By enacting changes in response, these control systems can improve efficiency in a wide range of systems, from industrial control through home automation to healthcare. For example, a set of smart sensors dotted around the body, can pick up on health problems that alert the user to a problem through their phone.



Author: Mark Zack, VP Global Semiconductors, Digi-Key

In industrial control, a series of sensors mounted along a production line can detect conditions that may lead to problems such as sudden changes in temperature or excess vibration that may signal a problem in a machine tool or a process going outside its bounds.
There are three fundamental components that combine to form an IoT node: intelligence, sensing, and wireless communications. Wireless connectivity is vital because it will allow sensor nodes to be deployed quickly and easily without the requirement to route network cables to each location.
In order to survive for long periods of time on a single battery charge, an IoT node needs to exhibit low power consumption. Typically, the node will be dormant for long periods of time, waking up for short periods to take a reading and then make a decision on whether to send out an alert based on the change or go back to sleep. A large number of microcontrollers are designed around this core requirement, sporting ultralow-energy sleep modes combined with high-performance instruction pipelines to streamline processing while awake.
A key decision is the type of architecture. A growing number of low-cost microcontrollers from vendors such as Atmel, Freescale, STMicroelectronics and Texas Instruments use 32-bit cores based on architectures such as ARM to deliver high performance at low power and access to a growing range of open-source software that allows applications to be built quickly. However, architectures such as Atmel’s AVR demonstrate that the 8-bit platform still provides a great deal of power, using advanced smart peripherals to collect data from sensor interfaces, and delivering high cost-effectiveness.
There are a number of possible approaches for introducing low-power communications to an IoT node, ranging from purpose-designed protocols such as Zigbee to low-power variants of Bluetooth and Wi-Fi. Some of these protocols offer direct compatibility with the internet protocol (IP). Others rely on a gateway to map between IP packets and the leaner protocols used by the IoT sensor nodes.

Zigbee is a low-power wireless network specification based on the IEEE 802.15.4 (2003) standard that was developed by a group of 16 companies involved in industrial and building automation. A novel aspect of Zigbee compared to many other networking protocols lies in its use of mesh networking. This allows IoT nodes far away from a central controller to use nodes in between to carry their communications. This not only extends the range of a central gateway, it also increases robustness as a transmission can use a number of different routes through the mesh.

Originally launched by Nokia as Wibree in 2006, Bluetooth Low-Energy (BLE) or Bluetooth Smart provides a similar range to classic Bluetooth but with reduced power consumption. In place of the 1MHz channels used by the original Bluetooth protocol, BLE uses a smaller set of wider-bandwidth channels of 2MHz but with a lower peak data rate.
The channel bandwidth is similar to that of Zigbee but with narrower spacing.
A key advantage of BLE is its lower latency, just 3ms versus the 100ms of classic Bluetooth, as well as lower complexity so that its software stack can easily be incorporated into lower-cost microcontrollers. BLE retains support for frequency hopping from the original Bluetooth protocol, which makes it more robust than Zigbee in the presence of strong interfering signals.

Figure 2: Channel arrangements for Zigbee, BluetoothLE and Wi-Fi.
One of the main application areas for BLE is medical instrumentation, where a number of on-body sensors to monitor heart rate, blood pressure, and posture relay their readings at regular intervals to a central controller, which may be a mobile phone or a dedicated medical instrument.
Having been in use in various forms for more than 15 years, Wi-Fi has the benefit of being the most mature wireless-networking radio technology suitable for IoT applications. Through protocols such as WPS, Wi-Fi can offer easy integration into an existing network for devices that have little to no physical user interface.
Of the wireless technologies suitable for IoT applications, Wi-Fi has the best power-per-bit transmission efficiency. Conventional Wi-Fi designs tend to use more energy to maintain a connection while quiescent than protocols such as BLE, which can decrease energy efficiency if the application does not need high bandwidth. However, vendors such as GainSpan have worked on power efficiency in designs such as the GS2000, which combines support for both ZigBee and Wi-Fi on the 2.4Ghz and 5GHz band. These designs put the radio into an energy-saving standby mode if the sensor node does not need to transmit any data. It wakes up only to send data or keep-alive connection packets used to assure central controllers that the node has not failed.
In general, Wi-Fi tends to suit applications where compliance with the IP stack is an advantage, there is a requirement to deliver large amounts of data, such as audio or video, or the remote devices can be powered by external energy sources.

An example of Wi-Fi in use is by Mernok Elektronik of South Africa, which used modules from connectBlue to incorporate wireless networking into the locomotive control and safety management systems of railway systems used in mining.
The modules are used to collect real-time operation data on each vehicle and provide a robust wireless connection across both 2.4GHz and 5GHz frequency bands with support for over-the-air firmware updates and parameter changes.

BLE and Wi-Fi can be used together efficiently as they both support coexistence protocols designed to reduce interference between the two on their common frequency band of 2.4GHz. This coexistence ability lends itself to implementation in gateway designs where BLE is used for connections to sensor nodes and Wi-Fi for relaying aggregated data to a backbone network.
The APx4 from Bluegiga provides an off-the-shelf solution for this, providing support for both Wi-Fi and the full Bluetooth 4.0 software stack that includes BLE, based around a powerful 450MHz ARM9 processor.
A number of integrated microcontrollers and support chipsets from vendors such as Atmel, CSR, Freescale, STMicroelectronics and Texas Instruments provide support for protocols such as BLE, Wi-Fi and ZigBee. For implementations that need flexibility, the configurable radio transceivers made by Lime Microsystems make it easier to deploy nodes that can be programmed with a specific RF interface personality at the point of manufacture to suit different networking needs in the target system.
As the IoT scales up, we can expect more integrated solutions to arrive on the market. But, even at this early stage of development, there are many choices available to the engineer with which to incorporate the three key components of IoT support.

www.digikey.com

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Silicon Labs Streamlines iOS Accessory Designs with Comprehensive 32-bit Development Kit

Silicon Labs introduced a new 32-bit hardware and firmware development kit designed to accelerate the design of Made for iPod/iPhone/iPad (MFi) accessories and help
product manufacturers get to market quickly.
Leveraging Silicon Labs’ ARM® Cortex®-M3-based SiM3U microcontroller (MCU), the MFI-SIM3U1XX-DK development kit supports the all-digital Lightning connector and protocol stack. The new development kit targets a wide range of accessories for iOS devices including entertainment accessories, device-powered dongles, game controllers and docking stations.
Silicon Labs designed the MFI-SIM3U1XX-DK kit as a turnkey solution to help developers simplify their Lightning-based accessory development projects and speed time to market while meeting the MFi program requirements with ease.
Silicon Labs’ 32-bit development kit provides an exceptionally cost-effective and comprehensive solution for accessory developers. The kit includes everything engineers need to begin developing Lightning-based accessories right away, including a hardware development board, firmware libraries and an example iOS App, which supports Appcessory-style communication between the iOS device and development board. By simplifying the development process, the new 32-bit kit enables MFi licensees to focus on what matters most – the accessory application itself.

The MFI-SIM3U1XX-DK kit enables developers to reduce the cost, complexity and power consumption of accessories designed for iOS devices. The SiM3U MCU features fully-specified analog peripherals, an integrated capacitive touch sense controller, an internal 5V regulator and crystal-less USB support, which eliminates the need for discrete crystal oscillators and reduces bill of materials (BOM) cost, component count and board space. Device-powered accessory applications benefit from the SiM3U MCU’s best-in-class power efficiency. The SiM3U MCU offers ultra-low power consumption with full analog operation down to 1.8 V, achieving a 33 percent lower active current than in-class competitors and a 5-100x lower sleep current, while a low-current USB idle mode ensures the viability of device-powered accessories.

Silicon Labs
www.silabs.com/mcu
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Energy Saving Network Power management (ES-NP)

To meet the European CO2 - emission guidelines, the car manufacturers have investigated all systems with respect to their energy efficiency. Even the smallest load can become a factor in deciding whether a tax of EUR 95 per 1g CO2/km has to be paid or not. Control units not required constantly are now - just like in mobile phones – intended to be put into current saving mode. Two competing network standards are vying for the developer’s attention namely the Pretended Network and the Partial Network. This article analyses each standard in terms of its respective advantages and disadvantages and offers solution approaches.



Figure 1

Challenge - the CO2 tax


Since 2012 everybody is talking about the European CO2 tax for cars. Every car manufacturer selling cars in the EU whose CO2 emission exceeds the regulation limits must pay penalty taxes. The intention behind this is make the industry and the consumers aware of the costs of climate changes and environmental damages caused by the CO2 emissions through a clear price adder.
The CO2 tax is being discussed in public controversially. Heated debates have ensued over the CO2 tax amount, its effectiveness, or the question whether CO2 tax is justified at all.
Actually, the CO2 tax has triggered a long due discussion over a problem, that is, to face the issues of limited resources and climate changes. Besides the emotional debate though, work is long under way to resolve the problems. The car manufacturers have analysed their car models and evaluated potential improvements already before 2012. In each construction segment like combustion engine, air drag, road resistance right up to electrical loads, potential improvements and corresponding costs have been calculated. From this point of view, the CO2 tax motivates innovation for economical processes and efficient use of energy.

Saving CO2 through control units


This article deals with the role of electronic control units which, assisted by the microcontrollers contribute significantly towards reduction of energy consumption in cars. In a typical premium vehicle up to 100 control units - interconnected in a network - are used to help increase the efficiency.
Some of which are active even when a car is parked (e.g. door control and anti-theft protection). In order to assess the increase in efficiency in this segment, the complete chain of factors impacting the efficiency must be reviewed (refer to figure 1).
One of the biggest loads in a control unit is the microcontroller which is powered by a voltage regulator. The voltage regulator in the control unit is powered by the dynamo, which in turn is driven by the combustion engine. This consumes fuel, exhausting thereby CO2. Therefore, the more current a microcontroller requires, the more fuel is consumed and consequently the vehicle exhausts more CO2.
A premium model with 100 control units has up to now been emitting up to 5g CO2/km purely due to the current consumption of the control electronic, NB without a single other electrical load e.g. the headlights or air conditioner ventilator being on. The CO2 tax envisages levying EUR 95 tax per 1g CO2/km per car if weight specific CO2 emission limit is exceeded. Thus, for an emission of 5g CO2/km, a car manufacturer would therefore have to pay up to EUR 475 CO2 tax.
Such assessments have increased awareness even for the smallest energy load. The development departments have been urged to put the control units in the current saving mode as often as possible or even to shut down completely. This idea has been copied from laptops and mobile phones where the displays are switched off and the CPU frequency is reduced if it is idle. Of course, the reduced current consumption is also always coupled with a reduced functionality and additionally the ramp-up time till full functionality is available again is long - just like in case of laptops. Whereas a trailer-light control unit can be switched off completely without any loss of comfort if no trailer is attached to the car; the situation is different though in case of an air conditioner ventilator. Therefore, the engineers must consider and control precisely as to when a control unit is not required in order to save energy at the expense its functionality.

Figure 2

Network of control units


Since in modern cars all control units communicate with each other via a network, the car manufacturers have created standards which define how much and at which point in time control unit current can be saved. One such Software-Standard-Platform is for example the AUTOSAR. Both approaches, namely the “Partial Network” and the “Pretended Network” were defined here.
Common to both approaches is that 2 current saving levels each have been specified. In Pretended Network the “Level 1” and “Level 2”; in Partial Network the “Standby” and “Sleep”. The higher the current reduction, the longer is the “wake-up” time of a control unit till it regains the full functionality (refer to figure 2).
Pretended Network
The Pretended Network follows the so-called Best Practice approach; the currents here - compared to the Partial Network – are even under extremely reduced use of resources very low, presently below 7mA (future target - below 2mA). The lower limit of the current is determined by the presently used standard transceiver which, with its 5mA has the largest share in the total standby current. Especially the volume producers appreciate the advantage that the new Pretended Network control units can operate together with the older units in the same network. This reduces the development risk considerably and also allows continual introduction of this technology within the next generation model. The wake-up time is considerably shorter than in Partial Network because the microcontroller is never fully powered off and the modern current saving modes of microcontroller can be utilized optimally.

Partial Network


Partial Network is the more radical of the two and is also a more expensive approach. A new type of intelligent network transceiver controls the whole control unit. Hereby, standby currents below 0.5 mA are feasible, but it is not a low cost solution. A complete implementation of this standard requires that all control units of a network must be equipped with the intelligent network-transceivers. Another disadvantage besides the additional costs is that the control unit wake-up time out of the maximum current saving mode is relatively long. This is because for the microcontroller it is almost like a cold-start process which can take up to 10 times as long as a warm-start.

Decision: Revolution or Evolution?


Every car manufacturer must ask himself the question: Revolution or evolution - Partial Network or the Pretended Network - or in other words - how much money and efforts one has to spend to achieve the respective CO2 reduction goal.
Thus, the question to be answered is - wouldn't the resources for an expensive network transceiver, additional efforts needed for converting the software of all network control units, and having to live with the slow reaction of the control unit in the maximum current saving mode – be better spent for something different?

Solution approach: Energy Saving Technologies (EST)


In parallel to the relatively recent debate over current saving due to European CO2 tax, Renesas has developed multiple technologies which reduce the current consumption of microcontrollers.
All in all 5 different solution approaches have been realised thereby:

ES-FT: “Energy Saving - Flash Technology”
ES-NP: “Energy Saving - Network Power Management”
ES-LPS: “Energy Saving - Low Power Sampler”
ES-PM: “Energy Saving - Power Modes”
ES-PS: “Energy Saving - Power Scaling”

The first two of these technologies would be reviewed more closely here for implementation in the “Partial Network" or the “Pretended Network".

Energy Saving Flash Technology (ES-FT)


Renesas has achieved a great success in its current 40 nm technology development for automotive microcontrollers with internal Flash.
Renesas developed indigenous transistor technology for its 32-bit microcontrollers, increasing performance while reducing the current consumption by 50% at the same time. This reduces the current consumption in operation mode itself by half, without one having to consider any functional limitation of the control units. This implies an efficiency growth by a factor of 2, a feat which only a few automotive construction segments might be able to duplicate.

Figure 3
Renesas did this by optimising the smallest unit of a microcontroller - the transistor. The total current consumption of a transistor is the sum of its dynamic and the static currents: The static currents are determined by leakage currents which flow as soon as power is applied to the transistor.
The dynamic current flows during switching of transistors, that is, when it changes its logical state (1 or 0).
These currents are determined by the internal capacities of the transistors.
Renesas has succeeded in reducing both by modifying the physical structure of the transistor. The internal transistor capacity was reduced by alteration of the oxide material, and by adapting the transistor geometry, the leakage current could be reduced by a factor of 10. These changes also resulted in higher operating frequencies.

Energy Saving Network Power Management (ES-NP)


In addition, Renesas has optimised the microcontroller digital structure in such a way that maximum current saving modes can be utilised (refer to figure 3), while at the same time the microcontroller can still react to external signals. This is totally taken care of by intelligent IPs (Peripherals) without any CPU interaction. Although in STOP mode the CPU is sleeping, the CAN-IP can participate in the network communication by itself in this configuration. The integrated intelligent message filters wake-up the CPU when a dedicated message type - which is configurable - is detected. Since here the microcontroller is only in STOP mode, it is only a matter of microseconds to execute a warm-start. After wake-up, the CPU can retrieve the message detected by the filter from the CAN-IP and process it.
This configuration is optimal for realising the “Pretended Network Level 2”: Renesas has tested this configuration in a real application and has thereby achieved an average current consumption of 1.58mA. With such a configuration the current consumption of a control unit which previously constantly consumed 105mA, has been reduced to a bare 6.5mA in current saving mode.
This translates into a reduction by 94%. There are no additional costs, no other control unit in network must be renewed and the control units wake-up from their current saving mode in a very short time.
The same configuration, with similar current consumption reduction can also be used to emulate the “Standby Mode” of a Partial Network. Though, in such case, one must live with the disadvantages of a Partial Network described above and that e.g. all network control units which are supposed to support the “Standby Mode” - must be adapted.

Figure 4

Conclusion and Outlook


There are many ways to reduce the current consumption and with that to reduce the CO2 emission. Renesas is of the opinion that an approach combining the latest microcontroller technology with the Pretended Network is the most efficient and the least risky way to reduce the current consumption of control units in cars with reasonable costs (refer to figure 4).
A similar higher demand would also trigger a further development of the last remaining large load; the CAN transceiver with its 5mA accounts for almost 80% of the standby current. With contemporary 0.5mA, control units with standby currents of 2mA in Pretended Network while still retaining all the advantages would then be feasible.
Already today, Renesas automotive series RH850/F1x microcontrollers offer full functionality with 50% less current consumption and the current saving in Pretended- or Partial Network applications is even higher, namely above 90%.

www.renesas.com
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Enabling a New Generation

The latest addition to Microchip’s PIC32 family increases performance, integration and connectivity.



Author: Bill Hutchings,Senior Product Marketing Manager, MCU32, Microchip Technology

If there is one characteristic that all modern devices strive to demonstrate - irrespective of the end-application - it is responsiveness. The ability to react ‘immediately’ is, of course, an illusion, sustained by the speed with which the microprocessor can respond to an event.
Improving the response time of a microprocessor is often closely influenced by the software it executes, however the underlying metric is the theoretical maximum number of instructions that can be executed per second, or MIPS, subsequently improving this figure has long been the driver for microprocessor evolution.
There are a number of recognised techniques for pushing performance up, as measured using the industry-standard unit of Dhrystone MIPS, or DMIPS. The latest member of the PIC32 family of high performance microcontrollers, the PIC32MZ, harnesses the latest MIPS32 core from Imagination Technologies, which successfully combines many of these techniques to deliver a device that increases performance threefold over its predecessor.
The core at the heart of the PIC32MZ is the recently announced MIPS microAptiv™ core, which features DSP extensions and the microMIPS® instruction set architecture, which allows a combination of 32- and 16-bit instructions to run from memory at near-full rate. In addition, the entire device is capable of running at up to 200MHz, which together results in a device that delivers 330 DMIPS; three times the performance of the PIC32MX family.
The microAptiv DSP extensions provide 159 additional instructions providing single-cycle access to the microarchitecture features that accelerate digital signal processing, such as multiply/accumulate. This means DSP algorithms can execute in as much as 75% fewer instruction cycles than the same algorithm executing on the PIC32MX. The PIC32MZ is the first family to use the microAptiv core, which as mentioned also introduces the microMIPS feature of 16-bit instructions, resulting in significantly higher code density; as much as 30% greater density than the PIC32MX.
The PIC32MZ is also capable of running at higher clock rates, up to 200MHz, which is around twice as fast as the PIC32MX. Together, these features deliver a threefold improvement in raw performance, allowing the PIC32MZ to address applications that demand faster response times when running ever-more complex software.

Built for Embedded Connectivity


The PIC32MZ integrates an Ethernet 10/100 MAC and PHY and it also features the highest ever number of serial channels offered in a PIC device. These features, coupled with a high performance core capable of running multiple protocol stacks simultaneously, makes it the most capable 32-bit MCU for applications targeting embedded connectivity. Another first for a PIC® microcontroller is the addition of an integrated Hi-Speed USB MAC/PHY, complemented by dual CAN ports, which further enforces the PIC32MZ’s connectivity credentials.
An important aspect of any connected device today is security and, here, the PIC32MZ offers a number of features designed to make embedded connectivity more secure. A full-featured hardware crypto engine, with a random number generator, provides high-throughput data encryption/decryption and authentication, such as AES, 3DES, SHA, MD5 and HMAC.
Beyond the high performance core and communications-oriented peripheral set, the PIC32MZ also features two further innovations never before offered in a PIC® microcontroller, both of which are intended to address emerging real-world needs of the target applications; both innovations deal with the need for more sophisticated memory systems.
An increasing number of OEMs are finding that the growing complexity of embedded software means in-field upgrades are becoming unavoidable. Instead of dismissing this trend as a development issue, manufacturers like Microchip are addressing the need head-on, by introducing innovative solutions to in-field software upgrades.
The PIC32MZ is at the leading edge of this effort, by integrating Dual-Panel Flash memory that allows a full software update to take place while the device is in service, executing program code at full speed. It achieves this by dividing the embedded Flash in to two physical and logical blocks, or panels. Each panel has its own charge pump and programming circuit, which means one panel is effectively ghost memory right up to the point when it becomes the main memory. As both panels essentially operate independently, one panel continues to operate at full speed while the other is updated in the background, without interrupting program execution.
Once the software update is installed and validated, the device can be reset and start executing memory from the newly programmed panel.
This feature allows a range of software issue to be addressed in the field without a service interruption, while also retaining the last known good software build in one panel at all times. The benefits of this innovation are far reaching; service calls will be minimised, service interruptions could be avoided entirely and software glitches could be resolved in near ‘real time’.
The other innovation intended to improve memory interfacing is the addition of an SQI port. SQI, or Serial Quad Interface, is a high-speed memory interface protocol that uses up to four wires, as opposed to the more common SPI or I2C interfaces which use only one pin for data exchange. The SQI interface uses a multiplexed bus to access 4-bits - or nibble - of memory at a time when accessing SQI-compatible memory devices, while still retaining SPI-compatibility.
The microAptiv core used in the PIC32MZ features an MMU (Memory Management Unit) and instruction and data caches, and up to 2048 KB of on chip flash and up to 512kbyte of SRAM, capable of supporting multiple protocol stacks running simultaneously, as well as buffer space to support audio processing, and frame buffers to support displays up to WQVGA resolution without the need for an external graphics chip.

Design Support


As the new PIC32MZ family is developed for high-end communications-oriented applications that need improved graphics, faster real-time performance and increased security, it is supported by a range of development kits that give full access to its advanced peripherals and crypto engine (for those family members that feature the optional crypto engine). These are further enhanced by a Multimedia Expansion Board II, Starter Kit Adapter and Plug-In Module which supports the Explore 16 Modular Development Board.
The latest addition to Microchip’s 32-bit MCU family drives performance, connectivity and security to new levels in embedded devices. With a threefold increase in raw processor performance, the addition of 159 DSP-specific instructions and innovative memory subsystem the PIC32MZ is well placed to enable a new generation of embedded devices.

www.microchip.com
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Microchip expands Arduino™ compatible chipKIT™ eco

Microchip announces the expansion of its Arduino™ compatible chipKIT™ ecosystem, with two new development tools from Digilent, Inc., and an embedded cloud software framework. Digilent’s chipKIT WF32 board minimises the need for users to purchase additional hardware or shields, by
integrating Microchip’s 32-bit PIC32MX695F512L MCU with Full Speed USB 2.0 Host/Device/OTG, its agency-certified MRF24WG0MA Wi-Fi® module and an energy-saving switch-mode power supply that employs Microchip’s MCP16301 DC-DC converter, in addition to a microSD card - all while maintaining an Arduino hardware-compatible form factor. Digilent’s chipKIT Motor Control Shield enables the development of applications using a wide variety of motor types, including servos, steppers and DCs, while allowing users to take advantage of the extra I/O pins found on many of the chipKIT development boards. This additional I/O provides added connectivity and more features than traditional, lower pin-count Arduino shields.
On the software side, an embedded cloud software framework enables designers to easily create “Internet of Things” (IoT) applications with the chipKIT WF32. Additionally, Digilent facilitates the rapid development of wireless HTTP server applications, via its comprehensive sample application that supports static pages loaded from the chipKIT WF32’s microSD card, as well as dynamically generated Web pages.
The combination of Digilent’s chipKIT WF32 base board and its HTTP server example application provides hobbyists, students and academics with an easy way to add wireless connectivity to
their Arduino projects.
This board also provides professional engineers with a rapid method for evaluating Wi-Fi in their embedded designs, and for creating embedded cloud computing services using Exosite. Additionally, as with all chipKIT base boards, the chipKIT WF32 can be connected to Microchip’s PICkit™ 3 programmer/debugger, allowing users to seamlessly move into Microchip’s professional MPLAB® X IDE and XC32 C and C++ compilers.
Robotics applications are particularly popular with hobbyists, students and academics, and their robots are driven by the motor types that the chipKIT Motor Control Shield is designed to support.
Microchip’s PIC32 MCUs enable a high level of integrated features and capabilities onto a single board, reducing development costs and complexity for hobbyists, academics and professional engineers.
Digilent’s chipKIT WF32 (TDGL021) priced at $69.99, and chipKIT Motor Shield (TDGL020) priced at $29.95, are both available today.

Microchip Technology
www.microchip.com/get/2T2W
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Freescale i.MX 6Quad Processor Enables Breakthrough OrCam Eyeglass-Mounted Device for the Visually Impaired

Designing with Freescale seminar in Israel includes product demonstration and keynote by OrCam co-founder, professor Amnon Shashua.



Freescale Semiconductor is powering a compelling new application from Israeli startup, OrCam, that helps people with visual impairments interact more easily with the world around them. The OrCam solution is a compact, eyeglass-mounted device that employs sophisticated computer vision algorithms running on Freescale’s high-performance, energy-efficient i.MX 6Quad applications processor to interpret visual inputs and communicate their meaning in real time to the person wearing the device.
Freescale’s i.MX 6Quad processor provides the OrCam product with the processing power required to execute highly advanced computer vision algorithms. The processor’s integrated camera interface reduces the end-product form factor by eliminating the need for additional components, and the chip’s advanced power management capabilities provide exceptional power efficiency for long battery life.
“The i.MX 6Quad processor delivered outstanding performance well within the power envelope we needed to design a wearable, affordable and intuitive solution for people whose visual impairments prevent them from easily interacting with the world around them,” said Amnon Shashua, co-founder of OrCam and the Sachs professor of computer science at the Hebrew University. “With Freescale’s highly advanced i.MX 6Quad device, OrCam is able to help compensate for lost vision and dramatically improve quality of life for the visually impaired.”

OrCam device powered by i.MX technology from Freescale. (Photo: Business Wire)
The OrCam product is comprised of a small unit mounted on the wearer’s eyeglasses and includes a small camera, microphone and bone conduction headphone. Designed with an intuitive user interface, the wearer simply points at an object or text with his or her finger, and the device then interprets and reads it.
The i.MX 6Quad processor integrates four ARM® Cortex™-A9 cores running up to 1.2 GHz, delivering the processing performance to handle the massive amounts of data captured by the OrCam product’s visual sensor. This performance allows execution of all processing algorithms and software speech codecs on a single chip. i.MX 6Quad processors support computer vision algorithms that allow OrCam to recognize a broad range of inputs, from the faces of friends who walk into a room, to text in newspapers and books, to transit signs, traffic signals and everyday objects of all sorts.
“This design win underscores Freescale’s role as a premier provider of embedded intelligence for the fast-growing wearables and intelligent healthcare markets,” said Shmuel Barkan, joint general manager and director of Sales and Marketing for Freescale Israel. “The i.MX 6Quad applications processor is fueling new categories of applications and, in this instance, is providing the processing power to enable a novel and extremely compelling product that is profoundly transforming the lives of people with visual impairments.”

Freescale Semiconductor
www.freescale.com
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Why choose when you can have both?

The latest mixed-signal controllers combine the best of both the analogue and digital power-conversion worlds, explains Stephen Stella, of Microchip Technology Inc.



Since the introduction of digital power conversion designers have had a clear choice between using analogue or digital for their designs. Each approach has its own distinct benefits as well as drawbacks, but the development of mixed-signal or hybrid controllers is making it possible for designers to combine the best of both power-conversion worlds.

Analogue for performance


The advantage of analogue power conversion is that it offers very efficient control, whilst the down-side is that it gives designers very little flexibility. Once the performance tradeoffs have been evaluated for each design, the chosen optimisation path is applied across the whole load profile and across the full power-conversion operating range.
Using this single level of optimisation across a design’s full power-conversion spectrum has been the industry standard for many years because, whilst it is inherently inflexible, it does deliver efficient control. However, recent government regulations, and the increasing expectations of end-users, are driving designers to achieve greater efficiency. This is pushing analogue power conversion to the limit of its efficiency and persuading many designers to make the change to digital power conversion.

Digital for flexibility


The main benefit of digital power conversion is that it offers the flexibility that analogue conversion lacks. It replaces one level of power-conversion optimisation with multi-point optimisation. It also provides the ability to communicate with the system, enabling power conversion to become part of the overall optimisation of the system’s long-term performance.
The disadvantage of digital power conversion is that this flexibility comes at the price. The digital approach increases system complexity because the analogue feedback from the system needs to be digitised before it can be used for power management. This means adding an analogue-to-digital converter, and also a high-speed microcontroller or digital signal processor to provide the processing power to achieve digital control.
The speed of the A/D conversion and the computational speed of the MCU/DSP determines the bandwidth of the digital control loop. So, if a design needs more bandwidth, it needs faster and more costly ADCs and MCUs.
Another factor is that digital-control techniques are very different to the techniques needed for analogue control. Making the switch from analogue to digital requires significant investment in the skills, resources, tools and processes required for digital design and software engineering. This investment can be a significant barrier to some companies.

The combined strength of hybrid controllers


Component manufacturers have addressed this dilemma by eliminating the choice between analogue and digital design with mixed-signal, or hybrid, controllers. Combining the strengths of both analogue and digital power conversion, hybrid controllers offset the weaknesses which are inherent in each approach. This enables designers to achieve the

Figure 1: Block diagram of the MCP19111 hybrid controller.
flexibility of a digital solution with the efficiency, load regulation and transient response of analogue power conversion. It also eliminates the need for designers to learn specialised skills or invest in new design resources and processes. Figure 1 shows the block diagram of Microchip’s MCP19111. This hybrid controller integrates a peak current-mode analogue controller with a small, 8-bit microcontroller. By performing power regulation in the analogue domain, the MCP19111’s integrated 8-bit microcontroller provides enough processing power to monitor and adjust the performance of the analogue controller.
Also on-board the MCP19111 are on-chip power MOSFET drivers and a mid-voltage LDO. This high level of integration enables the MCP19111 to significantly reduce the number of external components that are needed for power conversion whilst introducing a degree of flexibility that is not possible with analogue-only power conversion. A very wide operating voltage range of 4.5 to 32V operating range provides even more flexibility for the designer.
The introduction of hybrid or mixed-signal power conversion controllers offers designers the combination of the performance of analogue conversion, with the flexibility of digital control, at a cost that makes it accessible to a very wide range of applications. Whilst some designers will continue to make the choice and accept the limitations of analogue-only or digital-only power conversion, others will combine the best of both worlds by choosing the performance and flexibility of hybrid controllers.
www.microchip.com
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