The majority of users of brand-name measuring equipment probably think that top-class instruments are purchased by means of manufacturer’s trade representatives. Evolution of sales forms has also reached this group of products. Nowadays, to become an owner of a top class oscilloscope it is enough to click few times on a Website.
At present LeCroy appliances can be purchased in TME online shop ( www.tme.eu). The offer comprises of models belonging to several families differing by functional features, technical parameters, screen size and price. This simple form of a purchase does not deprive customers of technical support. Engineers dealing exclusively with measuring devices are always willing to help.

WaveAce
The first group comprises of WaveAce oscilloscopes that is exemplified by the WaveAce 224 model (TME symbol: LC-ACE224). WaveAce oscilloscopes represent a popular class, however, they are characterized by performance quality and multiple measuring functions. They are designed to perform basic measurements in construction laboratories and service stations. The maximum length of the record is equal to 20 kpoints/channel helps intercept in one release 2 or even 3 times more data than in cheaper oscilloscopes. The WaveAce 224A model is equipped with a colored LCD display with a 320 x 240 pixel matrix. This is a 4-channel oscilloscope with the analogue band of 200 MHz and sampling speed of 2 GSa/s (1 GSa/s for all channel, 50 GSa/s in the equivalent mode).
The display of oscillograms is a basic but not the only function of digital oscilloscopes. Every such device, regardless of the class, has also the possibility of making automatic measurements. WaveAce 224A measures simultaneously, in the real time, 32 parameters. Measuring functions are supplemented by cursor measurements and mathematical calculations, such as: sum, difference, product, quotient and FFT spectro analysis with four types of windows. If necessary, input functions are filtered by one of the four types of digital filters available for each channel. These are the following types of filters: low-pass, high-pass, mid-pass and middle-pass. In each channel, a filter limiting the band to up to 20 MHz can be switched on independently.
Pass/Fail Test available in the WaveAce 224A oscilloscope is used in manufacturing lines, commissioning and service work stations. Useful connection with the environment is provided by two USB interfaces (1×Device, 2×Host) and Ethernet.

WaveJet
The second type of LeCroy oscilloscopes available in TME are WaveJet appliances. In comparison to the WaveAce family, these are oscilloscopes offering higher measuring capabilities, but for a higher price. The WaveJet family can be represented by the WaveJet 324A model (TME symbol: LC-JET324A). The first visual element that is distinctive for these appliances is a bigger display equipped with a colored TFT LCD 640×480 pixel matrix (VGA). Parameters that should attract attention of users are: analogue band (in case of WaveJet 324A equal to 200 MHz) and sampling frequency of - 2 GSa/s (1 GSa/s for all channels and 100 GSa/s in the equivalent mode). However, in case of WaveJet family, a very characteristic parameter is the length of the record reaching as much as 500 kpoints for each channel. Such a long record enables interception in one acquisition of up to 250ms of the function for the highest sampling frequency. When compared to the WaveAce family, WaveJet oscilloscopes perform less automatic measurements. Furthermore, some of 26 parameters are defined in a slightly different manner. Technical data of devices provide more details. In WaveJet oscilloscopes, it is possible to use cursor measurements and mathematical calculations including the FFT analysis. Also, a 6-digit counter used to measure frequency of analysed functions operates independently. Special measuring mode (Replay Mode) facilitates detection of short-duration disturbances of glitch and runts types. They can be searched in the history of stored frames. The oscilloscope records them with the speed of 3600 frames per second.
Peak Detect acquisition facilitates trapping of even 1-nanosecond pins. Time base scopes provided for the Roll Mode - 50 ms/div...50 s/div (max. 100 kSa/s), on the contrary, help observe very slow functions.
The most commonly used mode of triggering present in all digital oscilloscopes is edge triggering. WaveJet 324A also makes impulse, impulse width, impulse counter and TV signal triggering available.
At present, a standard communication interface in digital oscilloscopes is USB. In WaveJet 324A, this is one device type port and one Host type port. Those ports are used to connect e.g. mass storage devices, PC’s and printers. Ethernet and GPIB interfaces are available as an option.
Oscilloscope handling is very simple. It is achieved by: multi-language menu, ergonomic location of control elements, hand wheels coupled with press-buttons. Appliance is ready for operation only after 3 seconds after its switching on. The selection of optimum operation parameters can be done manually or by entering settings recorded previously in a mass memory. The final solution is an AUTO SETUP button which starts automatic selection of the settings.

Wave Surfer
The third group of LeCroy oscilloscopes which is the strongest in TME’s range of products is the WaveSurfer family which is here represented by 24Xs. This oscilloscope is available under the TME symbol: WAVESURFER 24XS-A. The WaveSurfer family comprises of top tier appliances which are used for the most sophisticated measurements, but due to high price, are available to a narrow group of users.
A kind of surprise might be very economically designed front control panel, which is somehow in contradiction to declared measuring possibilities of the appliance. It results from the fact that mechanical elements constitute only a part of all control elements. It is because user’s interface uses also a touch screen constituting oscilloscope’s equipment. The 10,4” display with TFT LCD 800×600 pixel matrix (SVGA) which not only makes a visual impression, but also, in many cases, turns out to be essential during operation.
The WaveSurfer 24Xs oscilloscope as well as other models from this family, due to the implementation of special measuring functions, is particularly fit for analysis of signals on lines of many popular communication interfaces. The possibilities of the oscilloscope in this area can be proved by the richness of recognized protocols: SPI, I2C UART, RS232, USB, Audiobus (I2S, LJ, RJ, TDM), MIL-STD-1553, ARINC 429, MIPI D-PHY, DigRF, CAN and LIN. The moment of release can be set for particular events existing on interface lines, and their efficient analysis is ensured by the WaveScan Search and Find function. Data search is conducted by means of 20 methods. Finding a specific event is finished with the execution of a specific action. High record (5 Mpoints/channel) makes it possible to analyse a long period of time around the release point, even with the maximum sampling speed which for that oscilloscope is 2,5 GSa/s. The operation in WaveStream mode ensures a 256-level oscillograms brightness modulation, which makes an impression of watching them just like on an analogue oscilloscope.
The WaveSurfer oscilloscopes cooperate with high-impedance ZS series active probes ensuring correct observation of high-frequency functions, even up to 1 GHz. Probes are equipped with a number of various tips and also accessories ensuring proper grounding.
Just like in all digital oscilloscopes, WaveSurfer oscilloscope offers mathematical calculations, automatic and cursor measurements.
On the front panel there are separate hand wheels to operate cursors. The oscilloscope’s advantage is its ability to operate under Windows system control.
LeCroy is a brand recognized as a leading manufacturer of measuring instruments, including digital oscilloscopes. The appliances made by this manufacturer comprise of multiple, unique, own solutions that improve operation comfort of those complex devices.

More information available at:

Transfer Multisort Elektronik
Tel.: +48 42 645 54 44
Fax: +48 42 645 54 70
export@tme.eu
www.tme.eu

NFC (Near Field Communication) is a short-range contactless communication technology created by the combination of RFID and interconnection technologies.
NFC devices operate at 13.56Mhz frequency band with data transfer speed from 106 Kbit/s to 424 Kbit/s. the communication distance between two NFC devices is effective within 10 cm (in active communication mode), which helps to ensure the necessary level of security in transactions and communications.

by Wendy Du, Global Technology Centre, element14

Standards and Major Applications of NFC
So far the standards for NFC include ISO/IEC 18092 and ECMA-340, which are compatible with existing standards for contactless smart cards (MIFARE™ by Philips and FeliCa™ by SONY). ISO/IEC 18092 and ECMA-340 standards define two communication modes: active and passive. In active communication mode, initiator and target respectively generate their own RF field; while in passive communication mode, only the initiator provides an RF field (as shown in Figure 1).

These two modes use a different modulation scheme, coding scheme, transfer speed and frames’ format, as well as initialization process and requirements on data collision control during initialization. These are shown in the table below.

TRANSFER SPEED MODULATION CODING
106 Kbit/s 100% ASK Modified Miller
212 Kbit/s 8-30% ASK Manchester
424 Kbit/s 8-30% ASK Manchester

The AFE consists of an antenna and transceiver which is used to detect RF signals, as well as modulate and demodulate signals. A number of communication interfaces such as I2C, SPI and UART are used to communicate with the host controller and can be found on the transceiver. Generally, an NFC controller is a system-on-chip (SoC) that integrates the NFC transceiver and microcontroller, as well as the HCI (Host Controller Interface) and interfaces for connecting secure elements. Apart from ISO/IEC 18092 and ECMA-340 NFC protocols, a NFC controller may integrate other short-range contactless communication protocols in order to provide compatibility in different applications. The secure element is a smart card chip capable of storing multiple application programs. Programs related to mobile payment applications are stored in the chip. A smart card chip usually comprises a card management block, a security domain block (security domain includes the car issuer security domain and provider application security domain), and an application program management block.

According to the standards, NFC technology can be used in three application modes:

• Reader/writer mode
In this mode, NFC devices read information from electronic tags such as newspaper smart reading stands or posters.

• Peer-to-peer mode
In this mode, two NFC devices can exchange data such as synchronizing address books and exchanging images between themselves.

• Card emulation mode
In this mode, the NFC devices (e.g. cell phones) work as a traditional contactless smart card. This enables it to become a contactless paying and ticketing device. This mode is currently its most popular; NFC mobile payment is expected to become one of NFC’s major applications.

• NFC Mobile Payment Device Structure
Basically, a NFC device used in mobile payment has an AFE (Analog Front End), NFC controller and secure element.

NFC Mobile Payment Solutions

The hardware architectures of NFC-enabled products vary depending on different application requirements. The major differences lie in the placement of secure elements. One of them is that SIM cards are separated from secure elements. Another solution is to integrate secure elements in SIM cards. Currently, the former is the mainstream solution in the market; there is no need to integrate secure elements in SIM cards (as shown in Figure 2).
In other words, widespread adoption can be realized as long as semiconductor manufacturers and cell phone companies are willing to support NFC technology, without the need of mobile operators’ cooperation.
However, because the secure elements are not able to communicate with SIM cards directly, the information collected during NFC applications cannot be sent to remote devices such as servers in banks. If remote communication is required, a dedicated interface for the connection between NFC secure elements and baseband processors is necessary, resulting in an extreme complexity of hardware design and updating of the secure element’s application programs. Integrating secure elements and key data in the SIM cards is the solution that mobile operators prefer (as shown in Figure 3).
NFC controllers communicate with SIM cards by using SWP (Single Wire Protocol). SWP is a single-wire protocol with the capability of full-duplex communication achieved based on principle of voltage and load modulation. The application programs stored in secure elements can be downloaded and updated though over-the-air interfaces. As of this writing, NXP and ST have launched products optimized for mobile payment and TI and Renesas have announced that they will join in this market. A sampling of core chips is listed in the table below.

TRANSCEIVER CONTROLLER
Part No. Supplier Part No. Supplier
PN512 NXP PN531 NXP
PN513 NXP PN532 NXP
PN533 NXP
PN544 NXP
ST21NFCA ST

As more and more semiconductor suppliers and cell phone operators make their commitment to implementing NFC technology, the popularization of NFC technology will bring people around the globe unprecedented advantages in many aspects of their lives.

www.element14.com

By Ajinder Singh, Product Definition, Texas Instruments

High-end, cool smartphones and the ecosystem around them are symbolic of the fact that consumers want mobile broadband and applications that can help them connect to information, family and friends seamlessly. Thus, mobile broadband is clearly today's growth engine for the telecom industry.[1, 2] Telecom operators have seen huge growth in wireless data revenue in recent years despite the economic slow down. Meteoric growth in netbooks and HSDPA-USB dongles is also an indication that consumers want mobile broadband, not only in their homes and offices, but anywhere they go.
Missing in the mobile Internet today is the “wow” experience. Consumers still get discouraged by download speeds or degraded graphics while accessing data on their mobile devices. Applications such as video blogging and online gaming rely on faster connectivity and lower latency. Faster and reliable connectivity will help exploit the applications built around cloud computing and, thus, make our mobile office experience not limited by the mobile device’s hardware processing capability.
Mobile operators are counting on the fact that even now, out of the 4.3 billion wireless users, approximately 80 percent are voice-only GSM users. Thus, the growth opportunity over the next five to ten years is to capture three billion users who can subscribe to mobile broadband.[2] Growth can also potentially come from another set of devices like IPTV, digital cameras, etc., that have mobile broadband connectivity and can enable new services, generating more revenue for mobile operators.
To keep up with the surging demand to provide faster and reliable connectivity with lower latency, network operators around the world expect to roll out 4G networks, and long-term evolution (LTE) is the global front runner.
• Sometimes LTE also can be termed as fourth generation (4G), and is designed to increase the capacity and speed of mobile telephone networks. The LTE specification provides downlink (forward link) peak rates of at least 100 Mbps, an uplink (reverse link) of at least 50 Mbps, and radio access network (RAN) round-trip delays of less than 10 ms.[1]
• LTE also leverages advanced antenna technology concepts like beam forming to enable extended coverage. High peak-data rates can be achieved with multilayer antenna solutions such as 2×2 or 4×4 multiple-input multiple-outputs (MIMO).
Having all the great features of a new standard is one thing, but wireless and mobile network operators face the continuing challenge of investing capital and building networks that are somewhat “future-proof” in meeting the exploding demands on bandwidth. Network operators must choose the most cost-effective evolution of the networks towards 4G. Network upgrades required to deploy networks based on 4G standards like LTE must not only balance the limited availability of new spectrum, but also leverage existing spectrum.[3] To manage the evolving complexity of the standards efficiently, a concept of distributed open base station architecture has evolved in parallel with the standards to provide a flexible, cheaper and more scalable modular environment for managing the radio access evolution.
Traditional base station deployment as shown in Figure 1a requires the radio equipment control (REC) and radio equipment (RE) to be co-located with the antenna tower in a single enclosure. This approach proved to be detrimental to the network providers in terms of the large footprint, high power and ultimately high cost of its deployment.[6] This kind of architecture also leads to signal loss over the electrical cable that connects the antenna to the RE.
The distributed base station architecture (DBSA) in Figures 1b – 1c eliminates the dependency of the RF transceivers on the rest of the base station. This architecture allows the RE to be relocated next to their respective antennas, which minimizes the electrical loss between the RE and the antenna shown in Figure 1b, reducing the cost of RF power amplification. DBSA also allows various RE network topologies, for example chain, ring or tree as shown in Figure 1c. This approach ensures a relatively low network deployment footprint since the radio equipment can be networked with one another without requiring each RE to communicate to an REC.
The Open Base Station Architecture Initiative (OBSAI) and the Common Public Radio Interface (CPRI) standards address the baseband data communication between the radio equipment control and radio equipment, as well as radio equipment networking in DBSA. By standardizing the interface between REC and RE, the REC and RE equipment from different vendors can be mixed and matched. At the same time, a 2G/3G/4G-capable REC can communicate with different RE, thus allowing combined and concurrent multi-standard operations and reducing equipment upgrade needs.[3]
Both CPRI and OBSAI specify a high-speed serial interface between the radio equipment control and radio equipment, capable of baseband data transport (I/Q data), as well as communicating command/control and synchronization (for RE networking) information over the same interface.
Figure 2 shows signal flow in a DBSA. Looking at the RE in the forward link, the OBSAI/CPRI data is recovered by a serializer / deserializer (SerDes), which converts the high-speed serial data to parallel data and passes this data to an FPGA. The FPGA processes the OBSAI/CPRI logic and passes the I/Q baseband samples to a digital up-converter (dedicated logic), which modulates the I/Q baseband samples onto a digital IF carrier. The up-converted data is then passed through a data processing engine to reduce the crest factor (dedicated logic) and to digitally predistort (dedicated logic) the signal to compensate for side lobe generation in the power amplifier, as well as to ensure that the power amplifier can operate in the linear region.[4]
In the reverse link, the radio head contains all of the analog functionality to down-convert an RF band to an intermediate frequency and then digitally down-convert individual carriers to baseband in-phase and quadrature (I/Q) pairs of samples.
Multiplexed baseband samples (I/Q) along with control and management data in both the forward and reverse links are serialized and sent over the fiber optical cable via a SerDes device (for example, Texas Instruments’ TLK3134).[4]
Analyzing the DBSA with respect to the 4G evolution and the surge in demand to provide faster and more reliable data connectivity raises another concern. As the forward link and reverse link data rates increase and as more network subscribers move to high-bandwidth applications like on-demand TV, the serial data rate between the REC and RE also increases. The serial data rate (SDR) calculation between REC and RE[5] can be calculated using Equation 1:
[Equation 1]

Where,
SDR = Serial Data Rate between REC and RE
M = Number of antennas
Ac = Number of carriers/antenna
S = Sampling rate (sample/s/carrier)
N = Sample width, bits/sample
C = 8b10b overhead during serial transmission between REC and RE

Channel Bandwidth Sampling Rate
(MHz) (Msamples/s/carrier)
5 7.68
10 15.36
15 21.04
20 30.72

Table 1. Sampling rate required based on channel bandwidth

2(I/Q) = Multiplication factor of two to account for in-phase and quadrature-phase data
Using Equation 1 and Table 1, for a 20 MHz radio with four W-CDMA carriers, a two antenna system, sampling at 7.68 Msamples/s/carrier and with four bits/sample of I-Q sample width, the raw serial rate is shown in Equation 2:
[Equation 2]

Similarly, using Equation 1 and Table 1, for a four antenna LTE system, a one-carrier/antenna, 20 MHz LTE carrier sampling at 30.72 Msamples/s/carrier and with sample width of 16 bits/sample of I-Q data, the raw serial rate in Equation 3 is:
[Equation 3]
For an eight-antenna beam-forming LTE system, the SDR in Equation 3 would double to 9.8 Gbps. Hence, an increase in I-Q sample width, channel bandwidth, or number of antenna carriers directly contributes to an increase in the serial data rate between the REC and the RE. For network equipment manufacturers building infrastructure, it is important to realize that with the LTE evolution, the serial data rate must scale from modest rates of 614.4 Mbps to 9.8 Gbps or 12.2 Gbps. High SDR in the DBSA requires higher performance of the SerDes on both sides of the fiber optic cable for robust clock-data recovery and meeting the jitter specifications of the CPRI or OBSAI standards. To dig deeper into the SerDes and data processing expectations in 4G, let’s analyze the protocol stack of CPRI/OBSAI.
Figure 3a shows the CPRI protocol layer stack. Typically, the physical layer consists of fixed functionality, which is common across multiple protocols. The fixed functionality physical layer portion of the CPRI/OBSAI protocol layer is implemented as a hard macro to meet the stringent timing closure requirements. The logical layer, however, tends to be more customizable.[6] The logical layer is updated to keep up with emerging standard evolution, as well as the desire of network equipment manufacturers to create their own value-added features via proprietary functionality. An FPGA typically can provide the desired flexibility in implementing the logical layer portion of CPRI/OBSAI interface. The logic elements in an FPGA can be programmed to support a custom logical layer.
As network equipment manufacturers migrate towards the 4G deployment, they will face a situation where they still require not only the same flexibility to implement the logical layer, but also an increased SerDes performance to meet the increased SDR. Network equipment manufacturers have a choice either to buy an FPGA with integrated serdes or to buy an FPGA and discrete SerDes and interface them as shown in Figure 3b.
Let’s consider some of the key factors that can potentially determine the decision making of discrete SerDes-FPGA vs. integrated SerDes-FPGA:
• Cost of discrete SerDes + FPGA vs. Cost of FPGA with integrated SerDes
• Performance of a discrete SerDes vs. Performance of SerDes integrated in an FPGA
• Familiarity with a particular FPGA platform
• Area saving by moving to an FPGA with integrated SerDes.
Figure 4 shows an example where a 2G/3G/4G capable base-station or REC is connected to three RE serving three sectors. The three CPRI links in this example are configured at 614.4 Mbps, 3 Gbps and 9.8 Gbps line rates, assuming that 9.8 Gbps is the updated SDR to support 4G.

CASE A: Consider a case where the network equipment manufacturer is using an FPGA with a discrete SerDes and has invested time and resources in the learning cycle for that particular FPGA platform. To support 9.8 Gbps in such a case:
• The manufacturer upgrades the SerDes and continues to use the same familiar FPGA platform. Advantages: Gets economy of scale, since all three RE sectors as shown in Figure 4 can have a similar FPGA, while still operating at different SDRs. This way the manufacturer does not have to change the FPGA platform and go through a learning cycle.

CASE B: The network equipment manufacturer uses a cost-effective low-end FPGA with integrated SerDes capability. To support 9.8 Gbps in such a case, the manufacturer has three options:
• Move to a high-end FPGA (integrated SerDes) with 9.8 Gbps capability from a different vendor. Disadvantages: Costs more and the manufacturer must go through the learning cycle of the new FPGA platform.
• Move to an FPGA (integrated SerDes) with 9.8 Gbps capability from the same vendor that competes on price.
Disadvantage: Performance concern.
• Partition the system into FPGA + discrete SerDes, by buying an FPGA without SerDes from the same vendor.
Advantages: Manufacturer saves cost by moving to an FPGA without Serdes, still keeps the familiar FPGA platform, also as an example in Figure 4, can partition all three RE sectors with discrete SerDes and drive economy of scale by using the same FPGA. Disadvantage: Potentially more PCB area for a discrete Serdes and FPGA solution.

CASE C: The network equipment manufacturer is using a high-end FPGA with integrated Serdes. To support 9.8 Gbps in this case, the manufacturer has three options:
• Move to an FPGA (integrated SerDes) from the same vendor but with 9.8 Gbps capability. Disadvantages: The manufacturer might have to pay the very high cost of the FPGA with 9.8 Gbps SerDes capability.
• Move to a low-end FPGA (integrated SerDes) from a different vendor, but with 9.8 Gbps capability. Disadvantages: Learning cycle, performance concern, lack of economy of scale to drive the cost low.
• Partition the system into FPGA + discrete SerDes, by buying an FPGA without Serdes from the same vendor. Advantages: similar advantages as Case B.
At a high SDR like 9.8 Gbps or 12 Gbps, meeting the robust clock-data recovery, jitter-tolerance, signal-conditioning and signal-integrity requirements poses design challenges even for a discrete SerDes design, let alone for an FPGA-with-integrated-SerDes design where noise isolation of sensitive analog circuits from the digital logic elements block (majority area of the die) poses even greater challenges. At times, to meet the required performance, an FPGA with integrated SerDes can require expensive power supply filtering and use of a voltage controlled crystal oscillator vs. a less-expensive crystal oscillator. These requirements add to the cost of implementation. In summary, there is a cost associated with Serdes-integration into an FPGA, and that cost will potentially go up as integration challenges increase with high SDR. This is one of the primary reasons why even today, at 3 Gbps data rates or lower, an FPGA + discrete Serdes solution is more cost-effective compared to the integrated solution.

Conclusion
As network equipment manufacturers build up infrastructure for 4G there will be an ever-increasing demand for high serial data rates between the radio equipment control and radio equipment in distributed base station architecture deployment. This increased demand will require higher performance from Serdes on both sides of the fiber optic cable. Network equipment manufacturers can partition their system, so that for the logic layer processing, they can use the same familiar FPGA platform. To meet the high serial data rate, they can upgrade only the Serdes portion by moving to a discrete SerDes solution. This kind of partitioning will deliver the required performance and save the learning cycle of moving to a new FPGA platform, as well as helping drive economy of scale and ultimately saving cost for the manufacturers.

References
1. LTE – an introduction: Long Term Evolution (LTE) offers a superior user experience and simplified technology for next-generation mobile broadband (White Paper), Ericsson, June 2009.
2. LTE – Top 12 Challenges, by Manish Singh, Continuous Computing, Wireless Week, September 18, 2009.
3. Remote Radio Heads and the evolution towards 4G networks, by Christian F Lanzani, Georgios Kardaras, Deepak Boppana, Altera Corporation, February 2009:
4. WiMAX & Wireless Infrastructure Equipment block diagram, Texas Instruments 2009.
5. Using signal compression to ease migration to a 4G wireless infrastructure, by Allan Evans, Samplify Systems, Programmable Logic DesignLine, Oct 20, 2008.
6. Supporting CPRI-Based Wireless Basestations with Cost Optimized FPGAs, by Van Macomb and Ron Warner, Lattice Semiconductor Corporation, dspstore.com e-newsletter, March 2009.

About the Author
Ajinder Pal Singh is a Systems Engineer, Interface & Clock Products, at Texas Instruments where he is responsible for business development and product definition for telecommunications. Ajinder has presented several papers on high-speed interface signal integrity issues at IEEE conferences. He has one patent pending in the area of High Speed Interface. Ajinder earned his MSEE from Texas Tech, Lubbock, Texas.

www.ti.com

Texas Instruments introduce a new athlete to the embedded memory arena, called FRAM – ferroelectric random access memory, with amazing abilities. Looking at five disciplines we will compare this sportsman’s performance against his long time established Flash opponent. Before we go there let’s “x-ray” our two athletes to understand how they work.

By Matthias Poppel, Texas Instruments

How does FRAM work compared to Flash?
FRAM is built up similarly to DRAM consisting out of a transistor switching the current and a capacitor storing the information. Different is the capacitor’s dielectric which uses a ferroelectric material called Lead Zirconate Titanate, PZT. The term “ferroelectric” must not be confused with “ferromagnetic”. Only the relationship between voltage and charge of ferroelectric material looks similar to the hysteresis shape of ferromagnetic material. FRAM does not contain iron and is not susceptible to magnetic fields. In the presence of an electrical field a dipole inside the crystal gets formed by a shift of atoms and electronic charge along the direction of the field. The two possible polarization stages represent the logic “1” or “0”. FRAM is non-volatile as this polarization remains robustly even when the electrical field is removed. “Switching” the dipole is fast and requires only little energy.
A Flash memory cell - NOR Flash is typically used in microcontrollers - consists of a single MOSFET with two gates stacked on top of each other. The Control Gate switches the current from source to drain like in a normal NMOS transistor. The Floating Gate underneath the Control Gate is completely insulated by an oxide. Logic “1” is represented by no charge on the Floating Gate. Applying a threshold voltage to the Control Gate switches on the channel and flowing current can be measured. To program the cell to logic “0” a higher voltage, typically 12-14V, gets applied to the Control Gate. Now the source-drain current becomes high enough that some electrons jump through the oxide onto the Floating Gate.
This process is called hot-electron injection. The charge on the Floating Gate will drain the channel in a normal read operation so that not enough current can be measured to detect logic “1”. Erasing the Flash back to logic “0” - usually only possible in a block of cells called sector - gets achieved by applying the high programming voltage with opposite polarity causing electrons to move off the Floating Gate by quantum tunneling. Programming and erasing Flash memory takes some time and requires higher voltages that on-chip charge pumps provide from the supply voltage. Electrons on the Floating Gate containing the binary information stay there reliably for years but any weakness in the insulating oxide or physical effect by radiation for instance causing electrons to leak on or off the Floating Gate can cause a so called “bit flip”.

The FRAM Pentathlon
The universal athlete
Who in the embedded processing market doesn’t know the questions arising already at the beginning of a project when it comes to processor selection, and especially its memory configuration? How much non-volatile memory for program and data will we need? How big is the boot loader program? How much memory head room for additional features will we need, or shall we use external Flash and only on-chip SRAM? How much SRAM will we need at run time for the program, for data, as scratch pad? Do we have log data at high occurring frequencies that we want to constantly overwrite and do we need to allocate external EEPROM for that purpose?
With FRAM we now have a universal player, regardless whether Flash, SRAM, or EEPROM was used before. FRAM is non-volatile, it keeps its content after power down. The MSP430FR57xx family buffers enough on-chip energy to finalize a writing operation to memory even during loss of power thus maintaining a defined state. On top, designers do not have to worry about sector sizes and sector erase limitations as FRAM even offers bit programming. Designers are free to partition the entire on-chip memory according to their needs.

Almost no food
In an experiment we are writing data at a speed of 13kB per second to the FRAM of the MSP430FR5739 in one case and to the Flash of the MSP430F2274 in the other. Below diagram shows the current consumption needed in both cases.
Assuming 9uA compare to a single banana that our FRAM athlete needs to carry along as energy reservoir, to perform the same task the Flash opponent will have to carry a large backpack of 244 bananas. What a nice weight advantage that everybody who tried running in his life would appreciate.
Back to the embedded processing world this means additional significant power savings as memory access is an essential function in any microcontroller application. Main reason for the ultra low power memory operation is that FRAM needs little energy and gets programmed at 1.4V while Flash requires a charge pump to supply the programming voltages of 12-14V.

The 400m sprint champion
We are again comparing our two opponents from the previous experiment. Now we are writing 64bytes of data to the FRAM and Flash respectively, measuring the time needed. Writing to the memory of the MSP430FR5738 takes 1.6usec and flashing the memory of MSP430F5438 takes about 1.6msec. Flipping the dipole in the FRAM crystal is fast compared to driving charge through a thick oxide onto a floating gate.
To picture the difference, we put our two athletes into a 400m dash contest. Both are ready, hovering over the ground, awaiting the starter’s gun. At the signal, our Flash runner is still busy with his human reaction time and hasn’t yet left the starting block while the FRAM runner has almost finished his 3rd round. By the time the Flash runner is closing in on his first 400m lap – at world record speed – the FRAM runner has just passed one thousand laps.
Low power applications will benefit from this extremely fast write time as processor wake up periods can be shortened thus extending battery life time. Another advantage is saving time and money during in-line programming, where time to download code into the device can be significantly shortened.

The marathon
From the sprint we move to the endurance discipline. Flash write/erase cycles for embedded memory is limited to 10.000 cycles, in some exceptional cases to 100.000 cycles. FRAM however has a write endurance of at least 1014 cycles.
Trying to visualize the difference between those numbers we assume 105 cycles represent the endurance it takes to run a marathon of 42km. While our Flash runner takes on the distance between Marathon and Athens, the FRAM runner circles our planet along the equator, not only once but a million times.
The FRAM dipole mechanism is very robust and doesn’t show any wear effect at 1014 cycles. There are even studies showing this technology going beyond 1016 cycles. This write endurance is far more what any application requires from non-volatile memory today. However, Flash is not the only memory type FRAM needs to compete with. As we want to use FRAM also like SRAM as part of the universal memory we need to look at required SRAM cycles. In battery operated equipment for instance a 10% active duty cycle accessing the same memory location at 8Mhz would lead to a life time of about 8 years at 1014 cycles and to about 80 years at 1016 cycles.

The armored player
Our FRAM athlete is not only fast, perennial, and frugal when it comes to energy consumption but also very robust and armored like a football player.
As described above FRAM does not contain iron and is not ferromagnetic. FRAM therefore is not affected by magnetic fields. Susceptibility to electrical fields is also very low. Even a 50kV field in immediate proximity is not able to introduce enough voltage to impact the memory cell. The phenomenon of alpha particles, ions, cosmic, gamma, or x-rays causing a bit cell to flip to an opposite state is called “soft error”, and the occurring rate “Soft Error Rate” – SER. Any memory technology using charge on a capacitor can get affected. Not so for FRAM. It is unlikely that a particle will hit the FRAM dipole and change its polarization. Terrestrial SER for FRAM is not even measurable.

TI’s MSP430 ultra low power microcontroller goes FRAM
Embedded processing is not an individual sport. Every star player needs a team. Inserting FRAM into MSP430 microcontrollers augments this family’s low power, high performance DNA perfectly. The first MSP430FR57xx FRAM product line that is available now features the well known 16bit MSP430 core running at 24MHz consuming only 100uA/MHz. The fast FRAM write speeds at low power help even further reduce time periods the processor needs to stay awake thus extending battery life time or even enabling new applications like energy harvesting. The MSP430’s integrated high precision analog peripherals provide high flexibility to access and condition data that can be stored and continuously overwritten in FRAM. The MSP430FR57xx family comes in QFN and TSSOP packages, the QFN as small as 4mm × 4mm, all at a starting price of only $1.20 at 10ku.
First tool available is the MSP-EXP430FR5739 Experimenter Board, a platform that can help evaluate and drive development for data logging applications, energy harvesting, wireless sensing, automatic metering infrastructure (AMI) and many others for only $29. The tool incorporates a number of sensors and connectivity options including:
• 3 axis accelerometer
• NTC Thermister
• 8 Display LED's
• Footprint for additional through-hole LDR sensor
• 2 User input Switches
• Connection to most TI Wireless Daughter Cards (e.g. CC2520EMK)
The MSP430FR5739 device on the experimenter board can be powered and debugged via the integrated ezFET, or via TI Flash Emulation Tool, like the MSP-FET430UIF.

Conclusion
The score FRAM achieves in the memory Pentathlon of power consumption, write speed, write endurance, robustness, and unified use is so far beyond conventional memory types like Flash and EEPROM that it sets new benchmarks for battery powered, wireless connectivity, and data logging applications. The ultra-low-power, high performance 16bit MSP430 architecture is a perfect fit to be combined with FRAM. Its low standby currents, fast wake up times, and high performance core complement FRAM capabilities extremely well. The best at last, FRAM is already a market proven technology even in harsh environments. Since almost a decade FRAM gets manufactured by Ramtron and Texas Instruments.
www.ti.com

Today’s solid state lighting market is moving rapidly, as the demands of lighting control systems have changed from controlling luminance for a single LED to controlling three (RGB) or four (RGBW or RGBA) LEDs. The challenge that this brings with it is not only the control of luminance, but also that of color balance between the 3 or 4 LEDs within the lighting system. To help designers achieve this, Freescale Semiconductor has produced a lighting reference design consisting of both embedded hardware and a PC/Windows- based GUI, allowing color balance selection via either sRGB or CIE 1931 color spaces and direct control of the LEDs.

Source: Freescale Semiconductor

The embedded hardware consists of three printed circuit boards: the LED controller board, based on a Freescale ColdFire MCF52259 MCU, the LED driver board, based on a Freescale MC13213 MCU, delivering up to 1.5A of constant current per LED (max. 4) via the National Semiconductor LM3406, and the LED daughter-board, based on four (RGBW) Philips Lumileds Luxeon Rebel LEDs that plug into the LED driver board, complete with optical diffuser and reflector assembly.
In Figure 1, the LED controller board uses a USB interface (black cable shown top right) to connect to the PC-based lighting reference design GUI and also acts as a supply power to the LED controller board.

Software Overview

The software for the application consists of three parts:

The LightingDemo.exe application running on the PC.
The software running on the Controller board
The software running on the LED driver board

The software on the Controller and LED driver boards can be modified to use only the DMX-512A-RDM protocol, or only the DALI protocol.
Some source code files are shared between Controller and LED driver board implementations. For example, the file dmx_support.c contains support routines used by both boards for DMX-512.
DMX-512A and RDM implementation The DMX-512A protocol can be divided into two parts. In standard DMX-512A, each slave device has a start address in the range 1 - 512, and a footprint of one or more ‘slots’. Primary control is achieved by the controller broadcasting NULL Start-Code packets containing up to 512 slot values.
For added reliability, DMX-512A controllers can interleave the NULL Start-Code packets with System Information Packets (SIPs), which allow a checksum to be appended to the NULL Start-Code data.
The Remote Device Management protocol (RDM) is an extension to standard DMX-512A. It allows the controller to send multi-byte messages to an individual slave, and also to get multi-byte replies. In addition, it allows the controller to discover which devices are connected to the DMX-512A network.
The application software on the controller board implements both DMX-512A with SIP support, and RDM. RDM is used to find out which slave devices are connected, asks them for detailed information about their capabilities, and assigns DMX-512A start addresses.

See Freescale lighting reference design details

A DMX-512A/RDM slave consists of a Root device and optionally, one or more sub-devices. The LED driver board software implements one sub-device, used to control a single multi-color LED package. In principle, the software could easily be adapted to support multiple sub-devices.
The DMX-512A/RDM implementation on the LED driver board supports two RDM personalities:

(a) PERSONALITY_xyY_CONTROL When configured via RDM to use this personality, the LED driver board has a footprint of a single DMX-512A slot. The controller uses the slot to send a CIE 1931 Y luminance value (0 - 255), and sends the (x,y) chromaticity values using a separate RDM command.

(b) PERSONALITY_DIRECT_CONTROL In this personality, the LED driver board has a footprint of up to four DMX-512 slots, one for each channel that the LED supports. For example, a LED with three primaries Red, Green and Blue will have a footprint of three slots. The values in the DMX-512 slots are in the range 0-255 and correspond to 0 - 100% duty cycles.

DALI implementation on the Controller and Slave Boards On both controller and LED driver boards, DALI data is sent and received using a GPIO port. Data is sent using a routine which tightly controls the timing of the generated bi-phase signal to match the DALI specification.
Data is received by using an interrupt service routine which over-samples the signal. The signal has a frequency of 1200 bits per second, but it is bi-phase encoded, so there are 2400 phases per second. The interrupt frequency is 9600 sample per second, 4 samples per phase. Software compares the samples to ensure that they match. Because the received signal may vary slightly in frequency or duty cycle, software considers a match of 3, 4 or 5 samples to be acceptable.
The DALI protocol is really designed for controlling single-color lights, which it calls ‘ballasts’. The controller can instruct individual ballasts to light up, change to a specified power level and fade up or down. Ballasts can also be addressed as groups instead of individually, or added to pre-set scenes. The DALI protocol also includes a means for the controller to discover which DALI slaves are connected.
DALI commands from controller to slave are two bytes long, and replies from slave to controller are a single byte (many commands don’t result in a reply). Each DALI slave has a unique Short Address in the range 0 - 63.
The DALI implementation used by the controller and slave is standard in all respects except for one extension; the standard DALI protocol does not include any way for a controller to instruct a LED to change color rather than brightness, so a way is needed to achieve this. Since this is the way all DALI devices work, it is possible to use a Freescale DALI controller with non-Freescale DALI slaves, and it means that a Freescale slave looks like a standard ballast to non-Freescale controllers.
In order to convey chromaticity information, the Freescale implementation uses a backdoor route to extend the command set. The backdoor makes use of a standard DALI command DATA TRANSFER REGISTER and is invisible to non-Freescale DALI devices.
Because DALI commands are only two bytes long, all DALI slaves implement a Data Transfer Register (DTR). In order to program a setting such as the power-on level of a ballast, the DALI controller sends two 2-byte commands:

Store 99 in the DTR DATA TRANSFER REGISTER, 99

The backdoor command to set chromaticity information relies on the fact that setting the DTR to one value and then another (without any intervening commands), is both harmless and pointless. No other DALI controllers are likely to do it and it has no effect on normal DALI slaves.
In order to send chromaticity information, the controller sequences the DTR through a secret multi-character backdoor key to alert the LED driver that a chromaticity command is coming. It then uses the DTR to communicate the (x,y) chromaticity coordinates to the LED driver.

GUI Operation
When invoked, the lighting reference design GUI checks the status of a DALI/
DMX-512A switch on the LED controller board. This switch defines whether the DALI or DMX-512A interface will be used to communicate to any LEDs connected to the controller board. The DALI specification allows for a theoretical maximum of 125 LEDs to be attached, whereas the DMX-512A specification, as the name suggests, allows up for up to 512 LEDs to be controlled. The GUI will then scan the system to see how many LEDs are present.
Each LED daughter-board contains a thermistor placed as close as possible to the LED array. Using manufacturer-provided data, the LED junction temperatures can then be calculated on the MC13213 and the LED controller board can limit the power delivered to each LED to maximize LED lifetime. The real-time thermistor data is collected via the ADC module on the MC13213 and updated over DMX-512A/RDM around once a second.

The lighting reference design details—schematics, bill of materials, source code and PC-based software—are all available on either the Freescale website or element14.

www.element14.com
www.freescale.com

Medical systems utilize isolation to protect the operator, patient, the whole system or to separate noise from one part of the system to another. Where required for safety, isolation devices are governed by standards from groups such as UL and IEC; the appropriate standards are determined by the application. For example, IEC 60601 dictates safety requirements for medical devices, whereas IEC 60950 governs information technology equipment.

Within safety standards, there are certain terms related to the level or quality of isolation for medical systems:
Isolation Rating refers to the transient over voltage that the isolator can withstand. 2.5KVrms for 1 minute is a typical value, but medical systems may specify 5 KVrms for 1 minute.
Working Voltage refers to the continuous voltage applied across the isolation barrier. The isolation barrier in Working Voltage is expected to withstand this voltage over its operational life. Typical values are about 400Vrms.
Double Insulation refers to a device that has two indepen­dent systems of insulation.
Most standards today allow for a single system of isolation that has a reliability equivalent to two levels to be considered Double Insulation. These
terms are commonly used in UL safety standards.
Reinforced Isolation is similar to Double Insulation and is the term often found in IEC standards such as IEC 60601-1. Reinforced Isolation is often a requirement for medical system.
Creepage is the shortest distance along the surface of the package between two conductors on either side of the isolation barrier.
Clearance is the shortest distance through the air between two conductors. Medical applications that relate to patient safety typically require Reinforced Insulation, with a working voltage of 125Vrms or 250 KVrms, and Creepage and Clearance of at least 8mm.
The level of isolation is determined by how the system is partitioned. Figure 1 is a block diagram for a generic medical device, with various interfaces noted to show where isolation could be implemented. The patient must be isolated from the main system, so isolation for patient safety is required at points B, C or D. In many cases, D is not an option since a sensor or other device must be connected directly to the patient; in other cases, such as in ultrasound equipment, isolation at point D is provided by the plastic casing of the sensor head. The information at point C is still in the analog domain, so it is not cost-effective to isolate here, while maintaining accuracy. Therefore, isolation in medical equipment is often implemented at point B. That leaves the operator and peripherals unprotected, so isolation may also be used at the other interfaces as well. Medical safety standards allow for two types of isolation: Means of Patient Protection (MOPP) and Means of Operator Protection (MOOP). MOPP is governed by IEC 60601, whereas MOOP may be governed by less stringent requirements, such as IEC 60950. In the example above, the system may be partitioned so that Interface B requires IEC 60601 certification, whereas Interfaces A, E, F, and G may require only IEC 60950.
Some medical systems ensure the highest level safety by complying with IEC 60601 at all interfaces. In addition, the portion of the system connected to the patient may be considered a peripheral and connected to any one of the same ports, as shown at Interfaces E, F and G. IEC 60601 also provides safety against the use of highly charged defibrillators.
Without IEC 60601 certification, anything connected to a patient must be removed during defibrillation.

ISOLATING USB
Overall, USB has some considerable advantages over RS-232:

• Expandable to 127 peripherals
• Plug-and-play operation
• Hot-swap capability
• High data rates (1.5Mbit/s, 12Mbit/s, and 480Mbit/s)
• Industry standard compatibility
• Widespread use and availability on all PCs and laptops

Despite these advantages, adoption of USB in medical systems has not been as rapid as it has been in other consumer applications. What distinguishes these segments is the need for isolation. Despite the many advantages of USB over RS-232, isolating USB interfaces is not as straightforward as isolating other interfaces.
USB is difficult to isolate because it is differential, bidirectional, and requires configuration (via pull-up and pulldown) resistors to indicate bus speed. The bidirectional nature alone presents a significant challenge since there must be some means to determine the direction of the data transmission; in an isolated USB interface, this information must be passed across the isolation barrier. Flow of control is determined by data structures rather than by control signals.
The USB interface comprises 4 lines: VDD, D+, D–, VSS.
VDD is the 5V supply, VSS is ground, and D+ and D– are the differential signals. To complicate matters, D+ and D– can also be used to send single-ended data and are used to determine the state of the bus. Pull-up and pull-down resistors at the peripheral side of the bus set the speed of the USB interface and the idle state.
By definition, data can be transmitted at one of only three rates: 1.5Mbit/s (Low Speed), 12Mbit/s (Full Speed), and 480Mbit/s (High Speed).

The USB 2.0 standard supports all three data rates, whereas USB 1.1 supports only Low and Full Speed data rates. It is important to note that a device can be USB 2.0 compliant without supporting 480Mbit/s. Because standard optocouplers are, by nature, unidirectional, an isolated interface using optocouplers or other unidirectional isolators must first translate the USB signals into a set of unidirectional signals, as shown in Figure 2. Here, the D+/D– lines from a microcontroller are translated into single-ended, unidirectional SPI signals. These signals are isolated and then translated back into USB signals using a USB Serial Interface Engine, or USB controller. Instead of a simple, two-wire bus, this solution adds multiple components and increases the number of wires. The result is expensive, consumes considerable board space, and requires additional design time in part because the microcontroller requires software configuration.

ADuM4160 — USB ISOLATION IN A SINGLE PACKAGE
A simpler, more cost- and area-effective way to isolate USB is to use a dedicated USB isolator that can be inserted directly into the D+/D– USB signal path. The ADuM4160 provides Reinforced Isolation of up to 5KVrms with support for Low- and Full-Speed data rates. The ADuM4160 takes the functionality shown in Figure 2 and integrates it into a single package using Analog Devices’ iCoupler isolation technology. Unlike optocouplers, iCoupler isolators utilize planar transformers to transmit data across a 20μm thick polyimide insulation layer that can withstand up to 6KVrms. Data is transmitted by induction from one coil to the other. Figure 3 shows how rising and falling edges of a data stream are encoded as double or single 1ns pulses, respectively. These pulses are decoded on the receiver side to recreate the transmitted data.
iCoupler isolation has a number of benefits compared to optocouplers. The use of transformers allows data to be transmitted in either direction across the isolation barrier. Although the ADuM4160 uses dedicated transformers for transmit and receive signals, all coils are identical and contained within one package. Transformers are also inherently faster than the LED/phototransistor combination used in optocouplers. This allows iCoupler isolators to support the higher data rates and shorter propagation delays required by USB. iCoupler isolators also consume less power. The most critical advantage of iCoupler isolation, however, is the ability to integrate additional functionality. The space-saving benefits of iCoupler integration are shown in Figure 2, where the ADuM4160 consumes 75% less board space as compared to a multi- IC confi guration of USB transceivers and optocouplers.

BENEFITS OF ISOLATED USB
With a cost- and area-effective isolated USB solution that is easy to implement, medical applications may start to take advantage of the benefits of USB. In industrial systems, the lack of such an isolated USB solution forces USB to be used only for temporary connections; an operator can connect to the USB port only when the field side is disconnected. Isolated USB allows full time connection even during system operation.
In medical systems, isolated USB ports on home patient monitors can enable real-time connectivity between at-home patients and doctors to provide better, more accurate care. With isolated USB, such a home patient monitor can be connected to a personal computer, allowing real-time data transfer to a hospital via the Internet. With IEC 60601 medical grade safety approval, systems with isolated USB can even remain connected to patients during defibrillation.

www.farnell.com

Engineers and lighting designers have recognised for some time that a shift to LEDs as the primary light source for general lighting applications is just around the corner. Consumers, too, are beginning to become aware of this transition, with the first LED lamps for domestic use beginning to appear in the retail chain.
Expectations are high; having been persuaded, then forced by legislation, to abandon the incandescent lamp in favour of higher-efficiency products, users’ experience with compact fluorescent lamps was often less than satisfactory. Now, the message to those consumers is that LEDs will deliver long life, durability and efficiency, together with a pleasing spectral performance.

By Lee K. Koh, AMAD Marketing, Microchip Technology Inc.
General lighting – provision of ambient illumination for homes, offices and public spaces – is, in fact, somewhat lagging behind the pace of adoption of LEDs in a wide range of other applications. Some examples include automotive lighting for brake lights, running lights and, just starting to appear, headlights; architectural colour effect lighting; industrial, outdoor and street lighting; traffic and railway signals; and backlighting for LCD panels in televisions and monitors. In some of these applications, efficiency is paramount, by far the most important reason for moving to LEDs: in others, the main reason for their adoption lies with the flexibility given to designers of light fittings, when they no longer have to provide access to replace limited-life bulbs. In other cases it is the degree of control over the light, in terms of both hue and intensity, that appeals to lighting engineers.
Just as the CCFL changed the notion of a light source from a device that simply plugged into a supply, to one that required its own driver electronics package, so the advent of LEDs implies an associated page of driver and, in many cases, control circuitry. LEDs require constant-current drive. While a linear voltage regulator configured as a constant-current source may be acceptable for low-intensity applications, any design that majors on high light output and efficiency will demand a switch-mode supply. A number of common power supply topologies are useful for driving LEDs, including buck, boost, charge-pump, SEPIC, buck-boost and flyback, each with their own advantages in different circuit configurations. Many vendors including Microchip Technology offer dedicated driver ICs: a microcontroller can add intelligence to an application when paired with a driver IC; or the MCU can integrate the LED drive function, generating the drive waveforms and timing.
In the case of an application such as architectural effect lighting, the scope for using an MCU for setting precise levels to drive differently-coloured LEDs is clear. Perhaps less obvious is the issue of managing the production of white light, where an MCU is not just added intelligence, but is essential.
Single-source white LEDs are in fact blue light emitters, in which some of the blue light is used to energise a mix of phosphors that emits light in a range of colours from red through to green, to yield an overall white output. Many white LEDs cannot yield a high Colour Rendering Index (CRI), which is a measure of the ability of the light source to faithfully reproduce all colours. Systems with a better quality of white light can be created by mixing the light from two or more LED colours. The light output from each colour source drifts with age and temperature. This can be corrected and the overall light output – specific colour or Correlated Colour Temperature (CCT) – held constant by a feedback loop using a light sensor and a small MCU.
A range of small, inexpensive light sensors is available in the market. They typically comprise selectable colour filters – red, green, blue or none (white) – and a light-level sensor. The light sensor can supply intensity-level data to the MCU in a variety of ways. Light-to-voltage sensors send voltage levels to an Analogue-to-Digital Converter (ADC). Light-to-frequency sensors provide a variable frequency output, where the frequency is proportional to the amount of light. The pulse output from these sensors can be accumulated in a MCU timer to determine the light level. Light-to-digital sensors typically have a serial digital interface, such as I2C™.
Each type of sensor interface has unique advantages and requires different MCU resources (Figure 1).
In a complete closed loop colour-control system, the MCU must read the component colours from the light sensor, calibrate the light sensor output, and adjust the output of the individual LED drivers to achieve the desired colour. The choice of driver technique will depend on factors such as efficiency requirements, input voltage range, and the number of LEDs used.
Different methods may be used to control the driver output. The MCU can generate an analogue reference voltage using a Digital-to-Analogue Converter (DAC) or a digital potentiometer, and that voltage will directly set the LED drive current. Or, in an all-digital control chain, the MCU can provide pulse-width-modulated (PWM) signals that are used to modulate the driver output. The PWM signal can be used to enable/disable the driver itself, or it can be used to control a switch that disconnects the LEDs from the driver output.
If PWM control is used, the PWM frequency is chosen to be high enough so that the human eye cannot detect any flickering. This approach can be helpful if the application demands maximum efficiency; many LEDs deliver their peak efficiency (light output for a given current) at, or close to, their rated maximum. Delivering reduced light levels by a pulsed drive at the peak current level, rather than by a reduced constant current, will be more efficient.
The designer must decide how much control resolution is required in a colour control system, in order to select a MCU with the proper peripherals. For a Light-to-Voltage sensor, the measurement resolution of the on-chip ADC will be important. A Light to Frequency sensor requires an MCU timebase that can be incremented using an external clock. Light to Digital sensors will require an appropriate serial communications interface peripheral.
A MCU with multiple PWM peripherals is useful for controlling the individual LED dri­vers. In high resolution colour control systems, a PWM peripheral with 16 bits of control resolution or better is preferred. Serial communication peripherals, such as UARTs, SPI, I2C™, LIN and USB, enable input/output control and display functionality.
The designer will also have to determine the sample rate at which the control loop operates, and choose an MCU with appropriate computational resources. If the system is primarily concerned with maintaining a constant-white output as the LEDs age, then a relatively infrequent update rate will be required. LEDs of different colours will typically follow different light output curves as they age; but the will also do so in response to different drive levels. In variable-brightness, or dimming, applications, the colour-control loop must update to keep pace with the rate of change of brightness. One of the most demanding applications of this type is in selective dimming of LCD backlighting.
To enhance contrast in dark areas of a television picture, the backlighting in those areas is dimmed; but it must be maintained as a pure white in order that the LCD panel can continue to show the correct picture hue. In this case, a control loop update rate appropriate to the TV frame rate is required.
A device like the PIC24FJ16GA002, Figure 2, is a good candidate for the MCU in a colour-control system. The PIC24 device is available in small 28-pin packages with program memory ranging from 16 to 64KB and provides serial communication interfaces, 10-bit ADC and 5 PWM channels in one device.
The 16-bit MCU core easily handles the mathematics associated with the sensor calibration and colour control. The data output from the light sensor must be calibrated against a reference in order to provide consistent results.
The calibration process uses a Chroma Meter to mathematically correlate the output of the different colour LEDs and the spectral response and sensitivity of the light sensor to a standard colour-co-ordinate system, established in 1931 by the International Commission on Illumination (CIE), the CIE XYZ colour space. The calibration process generates a matrix of coefficients that must be stored in non-volatile memory with the luminary system and will be used to determine the difference between correlated and the desired output each pass through the control system.
Once calibrated, the MCU compares sensor data against desired co-ordinates on the CIE chromaticity plot and sets the drive values on each output channel until the correct CCT is achieved. As the control loop is operating in a dynamic environment, it is appropriate to use servo-type techniques; each channel has a PID (proportional-integral-derivative) algorithm that adjusts sensor data with the calibration values, evaluates the difference to target set-point and adjusts the output channels accordingly. As with any other closed-loop PID architecture, the algorithm runs continuously to reduce the error until the output CCT matches the set-point CCT. PID coefficients can be tuned to maximise the response of the system, but the rate of convergence to the set-point depends on the MCU’s efficiency in processing the mathematical demand.
As noted previously, some colour control systems may require faster processing and response time than others.
Systems that require an adjustable light source or one with high CRI (ability to render colours faithfully to the human eye) can have a wide range of user control requirements. A medical device with a graphical LCD display may have a tuneable LED backlight requiring the MCU to communicate to the LCD over SPI, as well as a touch-screen interface for adjusting the CCT and brightness. General illumination lighting for a commercial display case may require control from a central panel or computer to automatically adjust brightness, CCT and on/off based upon the time of day. Communication between these devices may be implemented using hard-wired serial bus protocols that are common in the lighting domain, such as DALI (Digital Addressable Lighting Interface, IEC 929) or DMX512 (a standard often seen in stage lighting and effects systems). Others may use a custom interface over USB or Ethernet.
When retrofitting advanced lighting systems to existing buildings, lighting designers are increasingly turning away from hard-wired infrastructure to wireless communications and a protocol such as ZigBee® for control. A MCU with flexible peripherals is an ideal host to implement the communication and user interfaces for these types of lighting applications.
LEDs as a general light source are set to make a dramatic impact on our lives, providing energy efficiency, compact size, portability, durability and long life. Multiple colour LEDs under the control of a small MCU will tune the light output, providing a very pleasant light that is suitable for the illuminated space. The MCU intelligently controls the driver circuit maximising efficacy, monitors conditions, and maximises energy efficiency and life expectancy.

References
- Microchip Application Note # AN1257, “Closed Loop Chromaticity Control: Interfacing a Digital RGB Color Sensor to a PIC24 MCU.” The application note and more information about “MCU Peripherals useful for LED Colour-Control Systems” can be found under “Colour Control Solutions” at Microchip’s online Intelligent Lighting Design Center, www.microchip.com/lighting
www.microchip.com

MSC now offers an extensively equipped RX62T motor control demonstration kit for brushless DC motors for just 119 euros.

The YRMCKITRX62T starter packet - based on the latest RX family of microcontrollers (MCUs) from Renesas, which is specifically tailored to the needs of modern drive controls - enables a simple and hence especially cost-effective development of highly-efficient drive systems.
With a CPU performance of 165 Dhrystone MIPS, a Floating Point Unit (FPU), two 12-bit A/D converters, comparators and two powerful timer units (MTU3 and GPT), the RX62T MCU is able to control brushless DC motors via highly-accurate vector control algorithms and at the same time take care of the power factor correction and communication interfaces. This ensures the highest precision and energy efficiency, even for requirements with rapid load changes. Furthermore, with the integrated CAN, LIN and SPI interfaces, the microcontroller can be easily networked with other units.
In order to relieve developers of as much work as possible, the kit includes the complete circuit diagrams and the whole source code for control of brushless motors. The user can thus choose between sensorless algorithms and applications with Hall sensors or encoders.
The kit is provided with a small 24V BLDC motor, which enables uncomplicated and quick initial tests. Matching to a specific motor type is achieved by simple changes to some software parameters. Since motor data such as speed, torque and phase currents can be displayed and evaluated in real-time with special PC software, an optimization of the control is possible without any great effort. With the optionally available E1 debugger, the supplied source code can be individually adapted and extended with own routines.
The integrated output stage allows the use of motors with up to 24V supply voltage. However, an external output stage for motors up to 400V, which is likewise available from Renesas, can also be connected.
www.msc-ge.com